From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Ajay Kaher <akaher@vmware.com>, Alexandre Ghiti <alexghiti@rivosinc.com>, Alexey Makhalov <amakhalov@vmware.com>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, Conor Dooley <conor.dooley@microchip.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, VMware PV-Drivers Reviewers <pv-drivers@vmware.com>, Will Deacon <will@kernel.org>, x86@kernel.org Subject: [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Date: Wed, 3 Apr 2024 01:04:33 -0700 [thread overview] Message-ID: <20240403080452.1007601-5-atishp@rivosinc.com> (raw) In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> It is a good practice to use BIT() instead of (1UL << x). Replace the current usages with BIT(). Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/sbi.h | 20 ++++++++++---------- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ef8311dafb91..4afa2cd01bae 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -233,20 +233,20 @@ enum sbi_pmu_ctr_type { #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF /* Flags defined for config matching function */ -#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) -#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) -#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) -#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) -#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) -#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) -#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) -#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) /* Flags defined for counter start function */ -#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) /* Flags defined for counter stop function */ -#define SBI_PMU_STOP_FLAG_RESET (1 << 0) +#define SBI_PMU_STOP_FLAG_RESET BIT(0) enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE = 0, diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index babf1b9a4dbe..a83ae82301e3 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -386,7 +386,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) cmask = 1; } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) { cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask = 1UL << (CSR_INSTRET - CSR_CYCLE); + cmask = BIT(CSR_INSTRET - CSR_CYCLE); } } -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Ajay Kaher <akaher@vmware.com>, Alexandre Ghiti <alexghiti@rivosinc.com>, Alexey Makhalov <amakhalov@vmware.com>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, Conor Dooley <conor.dooley@microchip.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, VMware PV-Drivers Reviewers <pv-drivers@vmware.com>, Will Deacon <will@kernel.org>, x86@kernel.org Subject: [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Date: Wed, 3 Apr 2024 01:04:33 -0700 [thread overview] Message-ID: <20240403080452.1007601-5-atishp@rivosinc.com> (raw) In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> It is a good practice to use BIT() instead of (1UL << x). Replace the current usages with BIT(). Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/sbi.h | 20 ++++++++++---------- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ef8311dafb91..4afa2cd01bae 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -233,20 +233,20 @@ enum sbi_pmu_ctr_type { #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF /* Flags defined for config matching function */ -#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) -#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) -#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) -#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) -#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) -#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) -#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) -#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) /* Flags defined for counter start function */ -#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) /* Flags defined for counter stop function */ -#define SBI_PMU_STOP_FLAG_RESET (1 << 0) +#define SBI_PMU_STOP_FLAG_RESET BIT(0) enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE = 0, diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index babf1b9a4dbe..a83ae82301e3 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -386,7 +386,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) cmask = 1; } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) { cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask = 1UL << (CSR_INSTRET - CSR_CYCLE); + cmask = BIT(CSR_INSTRET - CSR_CYCLE); } } -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-03 8:05 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-03 8:04 [PATCH v5 00/22] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 10:56 ` Andrew Jones 2024-04-04 10:56 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 02/22] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 10:57 ` Andrew Jones 2024-04-04 10:57 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 03/22] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:02 ` Andrew Jones 2024-04-04 11:02 ` Andrew Jones 2024-04-09 0:04 ` Atish Patra 2024-04-09 0:04 ` Atish Patra 2024-04-03 8:04 ` Atish Patra [this message] 2024-04-03 8:04 ` [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Atish Patra 2024-04-03 15:57 ` unsubscribe jonathan.oleson 2024-04-04 11:08 ` [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Andrew Jones 2024-04-04 11:08 ` Andrew Jones 2024-04-09 0:20 ` Atish Patra 2024-04-09 0:20 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 05/22] RISC-V: Add SBI PMU snapshot definitions Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:14 ` Andrew Jones 2024-04-04 11:14 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 06/22] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:52 ` Andrew Jones 2024-04-04 11:52 ` Andrew Jones 2024-04-10 22:29 ` Atish Patra 2024-04-10 22:29 ` Atish Patra 2024-04-11 7:45 ` Andrew Jones 2024-04-11 7:45 ` Andrew Jones 2024-04-04 12:01 ` Andrew Jones 2024-04-04 12:01 ` Andrew Jones 2024-04-09 0:21 ` Atish Patra 2024-04-09 0:21 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 07/22] drivers/perf: riscv: Fix counter mask iteration for RV32 Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:55 ` Andrew Jones 2024-04-04 11:55 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 08/22] RISC-V: KVM: Fix the initial sample period value Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:57 ` Andrew Jones 2024-04-04 11:57 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 09/22] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:59 ` Andrew Jones 2024-04-04 11:59 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 10/22] RISC-V: KVM: No need to update the counter value during reset Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 11/22] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 12:19 ` Andrew Jones 2024-04-04 12:19 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 12/22] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 11:23 ` Andrew Jones 2024-04-05 11:23 ` Andrew Jones 2024-04-09 0:33 ` Atish Patra 2024-04-09 0:33 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 13/22] RISC-V: KVM: Add perf sampling support for guests Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 11:36 ` Andrew Jones 2024-04-05 11:36 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 14/22] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:10 ` Andrew Jones 2024-04-05 12:10 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 15/22] RISC-V: KVM: Improve firmware counter read function Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:12 ` Andrew Jones 2024-04-05 12:12 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 16/22] KVM: riscv: selftests: Move sbi definitions to its own header file Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:16 ` Andrew Jones 2024-04-05 12:16 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 17/22] KVM: riscv: selftests: Add helper functions for extension checks Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:17 ` Andrew Jones 2024-04-05 12:17 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 18/22] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 19/22] KVM: riscv: selftests: Add SBI PMU extension definitions Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:20 ` Andrew Jones 2024-04-05 12:20 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 20/22] KVM: riscv: selftests: Add SBI PMU selftest Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:50 ` Andrew Jones 2024-04-05 12:50 ` Andrew Jones 2024-04-09 0:37 ` Atish Patra 2024-04-09 0:37 ` Atish Patra 2024-04-09 8:01 ` Andrew Jones 2024-04-09 8:01 ` Andrew Jones 2024-04-09 22:11 ` Atish Kumar Patra 2024-04-09 22:11 ` Atish Kumar Patra 2024-04-03 8:04 ` [PATCH v5 21/22] KVM: riscv: selftests: Add a test for PMU snapshot functionality Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 13:11 ` Andrew Jones 2024-04-05 13:11 ` Andrew Jones 2024-04-09 22:52 ` Atish Patra 2024-04-09 22:52 ` Atish Patra 2024-04-10 7:10 ` Andrew Jones 2024-04-10 7:10 ` Andrew Jones 2024-04-10 7:28 ` Atish Patra 2024-04-10 7:28 ` Atish Patra 2024-04-10 7:54 ` Andrew Jones 2024-04-10 7:54 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 22/22] KVM: riscv: selftests: Add a test for counter overflow Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 13:23 ` Andrew Jones 2024-04-05 13:23 ` Andrew Jones 2024-04-09 23:47 ` Atish Patra 2024-04-09 23:47 ` Atish Patra
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