From: Andrew Jones <ajones@ventanamicro.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: linux-kernel@vger.kernel.org,
"Clément Léger" <cleger@rivosinc.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Anup Patel" <anup@brainfault.org>,
"Ajay Kaher" <akaher@vmware.com>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Alexey Makhalov" <amakhalov@vmware.com>,
"Juergen Gross" <jgross@suse.com>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org,
"Mark Rutland" <mark.rutland@arm.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Shuah Khan" <shuah@kernel.org>,
virtualization@lists.linux.dev,
"VMware PV-Drivers Reviewers" <pv-drivers@vmware.com>,
"Will Deacon" <will@kernel.org>,
x86@kernel.org
Subject: Re: [PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name
Date: Thu, 4 Apr 2024 12:56:36 +0200 [thread overview]
Message-ID: <20240404-9c750d13d89168feb5ff34de@orel> (raw)
In-Reply-To: <20240403080452.1007601-2-atishp@rivosinc.com>
On Wed, Apr 03, 2024 at 01:04:30AM -0700, Atish Patra wrote:
> The counter overflow CSR name is "scountovf" not "sscountovf".
>
> Fix the csr name.
>
> Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
> Reviewed-by: Clément Léger <cleger@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> arch/riscv/include/asm/csr.h | 2 +-
> drivers/perf/riscv_pmu_sbi.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 2468c55933cd..9d1b07932794 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -281,7 +281,7 @@
> #define CSR_HPMCOUNTER30H 0xc9e
> #define CSR_HPMCOUNTER31H 0xc9f
>
> -#define CSR_SSCOUNTOVF 0xda0
> +#define CSR_SCOUNTOVF 0xda0
>
> #define CSR_SSTATUS 0x100
> #define CSR_SIE 0x104
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 8cbe6e5f9c39..3e44d2fb8bf8 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -27,7 +27,7 @@
>
> #define ALT_SBI_PMU_OVERFLOW(__ovl) \
> asm volatile(ALTERNATIVE_2( \
> - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \
> + "csrr %0, " __stringify(CSR_SCOUNTOVF), \
> "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
> THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
> CONFIG_ERRATA_THEAD_PMU, \
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: linux-kernel@vger.kernel.org,
"Clément Léger" <cleger@rivosinc.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Anup Patel" <anup@brainfault.org>,
"Ajay Kaher" <akaher@vmware.com>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Alexey Makhalov" <amakhalov@vmware.com>,
"Juergen Gross" <jgross@suse.com>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org,
"Mark Rutland" <mark.rutland@arm.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Shuah Khan" <shuah@kernel.org>,
virtualization@lists.linux.dev,
"VMware PV-Drivers Reviewers" <pv-drivers@vmware.com>,
"Will Deacon" <will@kernel.org>,
x86@kernel.org
Subject: Re: [PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name
Date: Thu, 4 Apr 2024 12:56:36 +0200 [thread overview]
Message-ID: <20240404-9c750d13d89168feb5ff34de@orel> (raw)
In-Reply-To: <20240403080452.1007601-2-atishp@rivosinc.com>
On Wed, Apr 03, 2024 at 01:04:30AM -0700, Atish Patra wrote:
> The counter overflow CSR name is "scountovf" not "sscountovf".
>
> Fix the csr name.
>
> Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
> Reviewed-by: Clément Léger <cleger@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> arch/riscv/include/asm/csr.h | 2 +-
> drivers/perf/riscv_pmu_sbi.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 2468c55933cd..9d1b07932794 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -281,7 +281,7 @@
> #define CSR_HPMCOUNTER30H 0xc9e
> #define CSR_HPMCOUNTER31H 0xc9f
>
> -#define CSR_SSCOUNTOVF 0xda0
> +#define CSR_SCOUNTOVF 0xda0
>
> #define CSR_SSTATUS 0x100
> #define CSR_SIE 0x104
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 8cbe6e5f9c39..3e44d2fb8bf8 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -27,7 +27,7 @@
>
> #define ALT_SBI_PMU_OVERFLOW(__ovl) \
> asm volatile(ALTERNATIVE_2( \
> - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \
> + "csrr %0, " __stringify(CSR_SCOUNTOVF), \
> "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
> THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
> CONFIG_ERRATA_THEAD_PMU, \
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
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next prev parent reply other threads:[~2024-04-04 10:56 UTC|newest]
Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-03 8:04 [PATCH v5 00/22] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-04 10:56 ` Andrew Jones [this message]
2024-04-04 10:56 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 02/22] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-04 10:57 ` Andrew Jones
2024-04-04 10:57 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 03/22] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-04 11:02 ` Andrew Jones
2024-04-04 11:02 ` Andrew Jones
2024-04-09 0:04 ` Atish Patra
2024-04-09 0:04 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-03 15:57 ` unsubscribe jonathan.oleson
2024-04-04 11:08 ` [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Andrew Jones
2024-04-04 11:08 ` Andrew Jones
2024-04-09 0:20 ` Atish Patra
2024-04-09 0:20 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 05/22] RISC-V: Add SBI PMU snapshot definitions Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-04 11:14 ` Andrew Jones
2024-04-04 11:14 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 06/22] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-04 11:52 ` Andrew Jones
2024-04-04 11:52 ` Andrew Jones
2024-04-10 22:29 ` Atish Patra
2024-04-10 22:29 ` Atish Patra
2024-04-11 7:45 ` Andrew Jones
2024-04-11 7:45 ` Andrew Jones
2024-04-04 12:01 ` Andrew Jones
2024-04-04 12:01 ` Andrew Jones
2024-04-09 0:21 ` Atish Patra
2024-04-09 0:21 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 07/22] drivers/perf: riscv: Fix counter mask iteration for RV32 Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-04 11:55 ` Andrew Jones
2024-04-04 11:55 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 08/22] RISC-V: KVM: Fix the initial sample period value Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-04 11:57 ` Andrew Jones
2024-04-04 11:57 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 09/22] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-04 11:59 ` Andrew Jones
2024-04-04 11:59 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 10/22] RISC-V: KVM: No need to update the counter value during reset Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 11/22] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-04 12:19 ` Andrew Jones
2024-04-04 12:19 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 12/22] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-05 11:23 ` Andrew Jones
2024-04-05 11:23 ` Andrew Jones
2024-04-09 0:33 ` Atish Patra
2024-04-09 0:33 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 13/22] RISC-V: KVM: Add perf sampling support for guests Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-05 11:36 ` Andrew Jones
2024-04-05 11:36 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 14/22] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-05 12:10 ` Andrew Jones
2024-04-05 12:10 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 15/22] RISC-V: KVM: Improve firmware counter read function Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-05 12:12 ` Andrew Jones
2024-04-05 12:12 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 16/22] KVM: riscv: selftests: Move sbi definitions to its own header file Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-05 12:16 ` Andrew Jones
2024-04-05 12:16 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 17/22] KVM: riscv: selftests: Add helper functions for extension checks Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-05 12:17 ` Andrew Jones
2024-04-05 12:17 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 18/22] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-03 8:04 ` [PATCH v5 19/22] KVM: riscv: selftests: Add SBI PMU extension definitions Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-05 12:20 ` Andrew Jones
2024-04-05 12:20 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 20/22] KVM: riscv: selftests: Add SBI PMU selftest Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-05 12:50 ` Andrew Jones
2024-04-05 12:50 ` Andrew Jones
2024-04-09 0:37 ` Atish Patra
2024-04-09 0:37 ` Atish Patra
2024-04-09 8:01 ` Andrew Jones
2024-04-09 8:01 ` Andrew Jones
2024-04-09 22:11 ` Atish Kumar Patra
2024-04-09 22:11 ` Atish Kumar Patra
2024-04-03 8:04 ` [PATCH v5 21/22] KVM: riscv: selftests: Add a test for PMU snapshot functionality Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-05 13:11 ` Andrew Jones
2024-04-05 13:11 ` Andrew Jones
2024-04-09 22:52 ` Atish Patra
2024-04-09 22:52 ` Atish Patra
2024-04-10 7:10 ` Andrew Jones
2024-04-10 7:10 ` Andrew Jones
2024-04-10 7:28 ` Atish Patra
2024-04-10 7:28 ` Atish Patra
2024-04-10 7:54 ` Andrew Jones
2024-04-10 7:54 ` Andrew Jones
2024-04-03 8:04 ` [PATCH v5 22/22] KVM: riscv: selftests: Add a test for counter overflow Atish Patra
2024-04-03 8:04 ` Atish Patra
2024-04-05 13:23 ` Andrew Jones
2024-04-05 13:23 ` Andrew Jones
2024-04-09 23:47 ` Atish Patra
2024-04-09 23:47 ` Atish Patra
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