From: Andrew Jones <ajones@ventanamicro.com> To: Atish Patra <atishp@rivosinc.com> Cc: linux-kernel@vger.kernel.org, Anup Patel <anup@brainfault.org>, Ajay Kaher <akaher@vmware.com>, Alexandre Ghiti <alexghiti@rivosinc.com>, Alexey Makhalov <amakhalov@vmware.com>, Conor Dooley <conor.dooley@microchip.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, VMware PV-Drivers Reviewers <pv-drivers@vmware.com>, Will Deacon <will@kernel.org>, x86@kernel.org Subject: Re: [PATCH v5 13/22] RISC-V: KVM: Add perf sampling support for guests Date: Fri, 5 Apr 2024 13:36:06 +0200 [thread overview] Message-ID: <20240405-5b84abdbf55142d40410fec8@orel> (raw) In-Reply-To: <20240403080452.1007601-14-atishp@rivosinc.com> On Wed, Apr 03, 2024 at 01:04:42AM -0700, Atish Patra wrote: > KVM enables perf for guest via counter virtualization. However, the > sampling can not be supported as there is no mechanism to enabled > trap/emulate scountovf in ISA yet. Rely on the SBI PMU snapshot > to provide the counter overflow data via the shared memory. > > In case of sampling event, the host first sets the guest's LCOFI > interrupt and injects to the guest via irq filtering mechanism defined > in AIA specification. Thus, ssaia must be enabled in the host in order > to use perf sampling in the guest. No other AIA dependency w.r.t kernel > is required. > > Reviewed-by: Anup Patel <anup@brainfault.org> > Signed-off-by: Atish Patra <atishp@rivosinc.com> > --- > arch/riscv/include/asm/csr.h | 3 +- > arch/riscv/include/asm/kvm_vcpu_pmu.h | 3 ++ > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kvm/aia.c | 5 ++ > arch/riscv/kvm/vcpu.c | 15 ++++-- > arch/riscv/kvm/vcpu_onereg.c | 5 ++ > arch/riscv/kvm/vcpu_pmu.c | 68 +++++++++++++++++++++++++-- > 7 files changed, 92 insertions(+), 8 deletions(-) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 9d1b07932794..25966995da04 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -168,7 +168,8 @@ > #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) > #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ > (_AC(1, UL) << IRQ_S_TIMER) | \ > - (_AC(1, UL) << IRQ_S_EXT)) > + (_AC(1, UL) << IRQ_S_EXT) | \ > + (_AC(1, UL) << IRQ_PMU_OVF)) > > /* AIA CSR bits */ > #define TOPI_IID_SHIFT 16 > diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h > index 77a1fc4d203d..257f17641e00 100644 > --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h > +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h > @@ -36,6 +36,7 @@ struct kvm_pmc { > bool started; > /* Monitoring event ID */ > unsigned long event_idx; > + struct kvm_vcpu *vcpu; > }; > > /* PMU data structure per vcpu */ > @@ -50,6 +51,8 @@ struct kvm_pmu { > bool init_done; > /* Bit map of all the virtual counter used */ > DECLARE_BITMAP(pmc_in_use, RISCV_KVM_MAX_COUNTERS); > + /* Bit map of all the virtual counter overflown */ > + DECLARE_BITMAP(pmc_overflown, RISCV_KVM_MAX_COUNTERS); > /* The address of the counter snapshot area (guest physical address) */ > gpa_t snapshot_addr; > /* The actual data of the snapshot */ > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index b1c503c2959c..e878e7cc3978 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_ZFA, > KVM_RISCV_ISA_EXT_ZTSO, > KVM_RISCV_ISA_EXT_ZACAS, > + KVM_RISCV_ISA_EXT_SSCOFPMF, > KVM_RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c > index a944294f6f23..0f0a9d11bb5f 100644 > --- a/arch/riscv/kvm/aia.c > +++ b/arch/riscv/kvm/aia.c > @@ -545,6 +545,9 @@ void kvm_riscv_aia_enable(void) > enable_percpu_irq(hgei_parent_irq, > irq_get_trigger_type(hgei_parent_irq)); > csr_set(CSR_HIE, BIT(IRQ_S_GEXT)); > + /* Enable IRQ filtering for overflow interrupt only if sscofpmf is present */ > + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF)) > + csr_write(CSR_HVIEN, BIT(IRQ_PMU_OVF)); > } > > void kvm_riscv_aia_disable(void) > @@ -558,6 +561,8 @@ void kvm_riscv_aia_disable(void) > return; > hgctrl = get_cpu_ptr(&aia_hgei); > > + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF)) > + csr_clear(CSR_HVIEN, BIT(IRQ_PMU_OVF)); > /* Disable per-CPU SGEI interrupt */ > csr_clear(CSR_HIE, BIT(IRQ_S_GEXT)); > disable_percpu_irq(hgei_parent_irq); > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index b5ca9f2e98ac..bb10771b2b18 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -365,6 +365,13 @@ void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) > } > } > > + /* Sync up the HVIP.LCOFIP bit changes (only clear) by the guest */ > + if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) { > + if (!(hvip & (1UL << IRQ_PMU_OVF)) && > + !test_and_set_bit(IRQ_PMU_OVF, v->irqs_pending_mask)) > + clear_bit(IRQ_PMU_OVF, v->irqs_pending); > + } > + > /* Sync-up AIA high interrupts */ > kvm_riscv_vcpu_aia_sync_interrupts(vcpu); > > @@ -382,7 +389,8 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) > if (irq < IRQ_LOCAL_MAX && > irq != IRQ_VS_SOFT && > irq != IRQ_VS_TIMER && > - irq != IRQ_VS_EXT) > + irq != IRQ_VS_EXT && > + irq != IRQ_PMU_OVF) > return -EINVAL; > > set_bit(irq, vcpu->arch.irqs_pending); > @@ -397,14 +405,15 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) > int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) > { > /* > - * We only allow VS-mode software, timer, and external > + * We only allow VS-mode software, timer, counter overflow and external > * interrupts when irq is one of the local interrupts > * defined by RISC-V privilege specification. > */ > if (irq < IRQ_LOCAL_MAX && > irq != IRQ_VS_SOFT && > irq != IRQ_VS_TIMER && > - irq != IRQ_VS_EXT) > + irq != IRQ_VS_EXT && > + irq != IRQ_PMU_OVF) > return -EINVAL; > > clear_bit(irq, vcpu->arch.irqs_pending); > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index f4a6124d25c9..4da4ed899104 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -36,6 +36,7 @@ static const unsigned long kvm_isa_ext_arr[] = { > /* Multi letter extensions (alphabetically sorted) */ > KVM_ISA_EXT_ARR(SMSTATEEN), > KVM_ISA_EXT_ARR(SSAIA), > + KVM_ISA_EXT_ARR(SSCOFPMF), > KVM_ISA_EXT_ARR(SSTC), > KVM_ISA_EXT_ARR(SVINVAL), > KVM_ISA_EXT_ARR(SVNAPOT), > @@ -101,6 +102,9 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext) > return false; > case KVM_RISCV_ISA_EXT_V: > return riscv_v_vstate_ctrl_user_allowed(); > + case KVM_RISCV_ISA_EXT_SSCOFPMF: nit: this case which starts with 'S' should come before the 'V' case since we tend to alphabetize these things. > + /* Sscofpmf depends on interrupt filtering defined in ssaia */ > + return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA); > default: > break; > } > @@ -116,6 +120,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) > case KVM_RISCV_ISA_EXT_C: > case KVM_RISCV_ISA_EXT_I: > case KVM_RISCV_ISA_EXT_M: > + case KVM_RISCV_ISA_EXT_SSCOFPMF: Since we can choose not to inject overflow interrupts for the guest, then the VMM could be allowed to disable this. Returning false from this function means that there's no way for KVM to turn off the behavior (or that KVM doesn't want to maintain code allowing the behavior to be turned off). Extensions that provides instructions which are unconditionally exposed to VS-mode can't be disabled, but anything KVM emulates, like this overflow can be. Is disabling Sscofpmf something that KVM would rather not maintain? Thanks, drew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com> To: Atish Patra <atishp@rivosinc.com> Cc: linux-kernel@vger.kernel.org, Anup Patel <anup@brainfault.org>, Ajay Kaher <akaher@vmware.com>, Alexandre Ghiti <alexghiti@rivosinc.com>, Alexey Makhalov <amakhalov@vmware.com>, Conor Dooley <conor.dooley@microchip.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, VMware PV-Drivers Reviewers <pv-drivers@vmware.com>, Will Deacon <will@kernel.org>, x86@kernel.org Subject: Re: [PATCH v5 13/22] RISC-V: KVM: Add perf sampling support for guests Date: Fri, 5 Apr 2024 13:36:06 +0200 [thread overview] Message-ID: <20240405-5b84abdbf55142d40410fec8@orel> (raw) In-Reply-To: <20240403080452.1007601-14-atishp@rivosinc.com> On Wed, Apr 03, 2024 at 01:04:42AM -0700, Atish Patra wrote: > KVM enables perf for guest via counter virtualization. However, the > sampling can not be supported as there is no mechanism to enabled > trap/emulate scountovf in ISA yet. Rely on the SBI PMU snapshot > to provide the counter overflow data via the shared memory. > > In case of sampling event, the host first sets the guest's LCOFI > interrupt and injects to the guest via irq filtering mechanism defined > in AIA specification. Thus, ssaia must be enabled in the host in order > to use perf sampling in the guest. No other AIA dependency w.r.t kernel > is required. > > Reviewed-by: Anup Patel <anup@brainfault.org> > Signed-off-by: Atish Patra <atishp@rivosinc.com> > --- > arch/riscv/include/asm/csr.h | 3 +- > arch/riscv/include/asm/kvm_vcpu_pmu.h | 3 ++ > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kvm/aia.c | 5 ++ > arch/riscv/kvm/vcpu.c | 15 ++++-- > arch/riscv/kvm/vcpu_onereg.c | 5 ++ > arch/riscv/kvm/vcpu_pmu.c | 68 +++++++++++++++++++++++++-- > 7 files changed, 92 insertions(+), 8 deletions(-) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 9d1b07932794..25966995da04 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -168,7 +168,8 @@ > #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) > #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ > (_AC(1, UL) << IRQ_S_TIMER) | \ > - (_AC(1, UL) << IRQ_S_EXT)) > + (_AC(1, UL) << IRQ_S_EXT) | \ > + (_AC(1, UL) << IRQ_PMU_OVF)) > > /* AIA CSR bits */ > #define TOPI_IID_SHIFT 16 > diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h > index 77a1fc4d203d..257f17641e00 100644 > --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h > +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h > @@ -36,6 +36,7 @@ struct kvm_pmc { > bool started; > /* Monitoring event ID */ > unsigned long event_idx; > + struct kvm_vcpu *vcpu; > }; > > /* PMU data structure per vcpu */ > @@ -50,6 +51,8 @@ struct kvm_pmu { > bool init_done; > /* Bit map of all the virtual counter used */ > DECLARE_BITMAP(pmc_in_use, RISCV_KVM_MAX_COUNTERS); > + /* Bit map of all the virtual counter overflown */ > + DECLARE_BITMAP(pmc_overflown, RISCV_KVM_MAX_COUNTERS); > /* The address of the counter snapshot area (guest physical address) */ > gpa_t snapshot_addr; > /* The actual data of the snapshot */ > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index b1c503c2959c..e878e7cc3978 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_ZFA, > KVM_RISCV_ISA_EXT_ZTSO, > KVM_RISCV_ISA_EXT_ZACAS, > + KVM_RISCV_ISA_EXT_SSCOFPMF, > KVM_RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c > index a944294f6f23..0f0a9d11bb5f 100644 > --- a/arch/riscv/kvm/aia.c > +++ b/arch/riscv/kvm/aia.c > @@ -545,6 +545,9 @@ void kvm_riscv_aia_enable(void) > enable_percpu_irq(hgei_parent_irq, > irq_get_trigger_type(hgei_parent_irq)); > csr_set(CSR_HIE, BIT(IRQ_S_GEXT)); > + /* Enable IRQ filtering for overflow interrupt only if sscofpmf is present */ > + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF)) > + csr_write(CSR_HVIEN, BIT(IRQ_PMU_OVF)); > } > > void kvm_riscv_aia_disable(void) > @@ -558,6 +561,8 @@ void kvm_riscv_aia_disable(void) > return; > hgctrl = get_cpu_ptr(&aia_hgei); > > + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF)) > + csr_clear(CSR_HVIEN, BIT(IRQ_PMU_OVF)); > /* Disable per-CPU SGEI interrupt */ > csr_clear(CSR_HIE, BIT(IRQ_S_GEXT)); > disable_percpu_irq(hgei_parent_irq); > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index b5ca9f2e98ac..bb10771b2b18 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -365,6 +365,13 @@ void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) > } > } > > + /* Sync up the HVIP.LCOFIP bit changes (only clear) by the guest */ > + if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) { > + if (!(hvip & (1UL << IRQ_PMU_OVF)) && > + !test_and_set_bit(IRQ_PMU_OVF, v->irqs_pending_mask)) > + clear_bit(IRQ_PMU_OVF, v->irqs_pending); > + } > + > /* Sync-up AIA high interrupts */ > kvm_riscv_vcpu_aia_sync_interrupts(vcpu); > > @@ -382,7 +389,8 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) > if (irq < IRQ_LOCAL_MAX && > irq != IRQ_VS_SOFT && > irq != IRQ_VS_TIMER && > - irq != IRQ_VS_EXT) > + irq != IRQ_VS_EXT && > + irq != IRQ_PMU_OVF) > return -EINVAL; > > set_bit(irq, vcpu->arch.irqs_pending); > @@ -397,14 +405,15 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) > int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) > { > /* > - * We only allow VS-mode software, timer, and external > + * We only allow VS-mode software, timer, counter overflow and external > * interrupts when irq is one of the local interrupts > * defined by RISC-V privilege specification. > */ > if (irq < IRQ_LOCAL_MAX && > irq != IRQ_VS_SOFT && > irq != IRQ_VS_TIMER && > - irq != IRQ_VS_EXT) > + irq != IRQ_VS_EXT && > + irq != IRQ_PMU_OVF) > return -EINVAL; > > clear_bit(irq, vcpu->arch.irqs_pending); > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index f4a6124d25c9..4da4ed899104 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -36,6 +36,7 @@ static const unsigned long kvm_isa_ext_arr[] = { > /* Multi letter extensions (alphabetically sorted) */ > KVM_ISA_EXT_ARR(SMSTATEEN), > KVM_ISA_EXT_ARR(SSAIA), > + KVM_ISA_EXT_ARR(SSCOFPMF), > KVM_ISA_EXT_ARR(SSTC), > KVM_ISA_EXT_ARR(SVINVAL), > KVM_ISA_EXT_ARR(SVNAPOT), > @@ -101,6 +102,9 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext) > return false; > case KVM_RISCV_ISA_EXT_V: > return riscv_v_vstate_ctrl_user_allowed(); > + case KVM_RISCV_ISA_EXT_SSCOFPMF: nit: this case which starts with 'S' should come before the 'V' case since we tend to alphabetize these things. > + /* Sscofpmf depends on interrupt filtering defined in ssaia */ > + return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA); > default: > break; > } > @@ -116,6 +120,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) > case KVM_RISCV_ISA_EXT_C: > case KVM_RISCV_ISA_EXT_I: > case KVM_RISCV_ISA_EXT_M: > + case KVM_RISCV_ISA_EXT_SSCOFPMF: Since we can choose not to inject overflow interrupts for the guest, then the VMM could be allowed to disable this. Returning false from this function means that there's no way for KVM to turn off the behavior (or that KVM doesn't want to maintain code allowing the behavior to be turned off). Extensions that provides instructions which are unconditionally exposed to VS-mode can't be disabled, but anything KVM emulates, like this overflow can be. Is disabling Sscofpmf something that KVM would rather not maintain? Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-04-05 11:36 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-03 8:04 [PATCH v5 00/22] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 10:56 ` Andrew Jones 2024-04-04 10:56 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 02/22] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 10:57 ` Andrew Jones 2024-04-04 10:57 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 03/22] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:02 ` Andrew Jones 2024-04-04 11:02 ` Andrew Jones 2024-04-09 0:04 ` Atish Patra 2024-04-09 0:04 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-03 15:57 ` unsubscribe jonathan.oleson 2024-04-04 11:08 ` [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Andrew Jones 2024-04-04 11:08 ` Andrew Jones 2024-04-09 0:20 ` Atish Patra 2024-04-09 0:20 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 05/22] RISC-V: Add SBI PMU snapshot definitions Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:14 ` Andrew Jones 2024-04-04 11:14 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 06/22] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:52 ` Andrew Jones 2024-04-04 11:52 ` Andrew Jones 2024-04-10 22:29 ` Atish Patra 2024-04-10 22:29 ` Atish Patra 2024-04-11 7:45 ` Andrew Jones 2024-04-11 7:45 ` Andrew Jones 2024-04-04 12:01 ` Andrew Jones 2024-04-04 12:01 ` Andrew Jones 2024-04-09 0:21 ` Atish Patra 2024-04-09 0:21 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 07/22] drivers/perf: riscv: Fix counter mask iteration for RV32 Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:55 ` Andrew Jones 2024-04-04 11:55 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 08/22] RISC-V: KVM: Fix the initial sample period value Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:57 ` Andrew Jones 2024-04-04 11:57 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 09/22] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 11:59 ` Andrew Jones 2024-04-04 11:59 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 10/22] RISC-V: KVM: No need to update the counter value during reset Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 11/22] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-04 12:19 ` Andrew Jones 2024-04-04 12:19 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 12/22] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 11:23 ` Andrew Jones 2024-04-05 11:23 ` Andrew Jones 2024-04-09 0:33 ` Atish Patra 2024-04-09 0:33 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 13/22] RISC-V: KVM: Add perf sampling support for guests Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 11:36 ` Andrew Jones [this message] 2024-04-05 11:36 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 14/22] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:10 ` Andrew Jones 2024-04-05 12:10 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 15/22] RISC-V: KVM: Improve firmware counter read function Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:12 ` Andrew Jones 2024-04-05 12:12 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 16/22] KVM: riscv: selftests: Move sbi definitions to its own header file Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:16 ` Andrew Jones 2024-04-05 12:16 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 17/22] KVM: riscv: selftests: Add helper functions for extension checks Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:17 ` Andrew Jones 2024-04-05 12:17 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 18/22] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-03 8:04 ` [PATCH v5 19/22] KVM: riscv: selftests: Add SBI PMU extension definitions Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:20 ` Andrew Jones 2024-04-05 12:20 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 20/22] KVM: riscv: selftests: Add SBI PMU selftest Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 12:50 ` Andrew Jones 2024-04-05 12:50 ` Andrew Jones 2024-04-09 0:37 ` Atish Patra 2024-04-09 0:37 ` Atish Patra 2024-04-09 8:01 ` Andrew Jones 2024-04-09 8:01 ` Andrew Jones 2024-04-09 22:11 ` Atish Kumar Patra 2024-04-09 22:11 ` Atish Kumar Patra 2024-04-03 8:04 ` [PATCH v5 21/22] KVM: riscv: selftests: Add a test for PMU snapshot functionality Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 13:11 ` Andrew Jones 2024-04-05 13:11 ` Andrew Jones 2024-04-09 22:52 ` Atish Patra 2024-04-09 22:52 ` Atish Patra 2024-04-10 7:10 ` Andrew Jones 2024-04-10 7:10 ` Andrew Jones 2024-04-10 7:28 ` Atish Patra 2024-04-10 7:28 ` Atish Patra 2024-04-10 7:54 ` Andrew Jones 2024-04-10 7:54 ` Andrew Jones 2024-04-03 8:04 ` [PATCH v5 22/22] KVM: riscv: selftests: Add a test for counter overflow Atish Patra 2024-04-03 8:04 ` Atish Patra 2024-04-05 13:23 ` Andrew Jones 2024-04-05 13:23 ` Andrew Jones 2024-04-09 23:47 ` Atish Patra 2024-04-09 23:47 ` Atish Patra
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20240405-5b84abdbf55142d40410fec8@orel \ --to=ajones@ventanamicro.com \ --cc=akaher@vmware.com \ --cc=alexghiti@rivosinc.com \ --cc=amakhalov@vmware.com \ --cc=anup@brainfault.org \ --cc=atishp@rivosinc.com \ --cc=conor.dooley@microchip.com \ --cc=jgross@suse.com \ --cc=kvm-riscv@lists.infradead.org \ --cc=kvm@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-kselftest@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=mark.rutland@arm.com \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=pbonzini@redhat.com \ --cc=pv-drivers@vmware.com \ --cc=shuah@kernel.org \ --cc=virtualization@lists.linux.dev \ --cc=will@kernel.org \ --cc=x86@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.