From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>,
Heiko Stuebner <heiko@sntech.de>,
Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v3 10/17] RISC-V: define the elements of the VCSR vector CSR
Date: Sat, 20 Apr 2024 18:04:42 -0700 [thread overview]
Message-ID: <20240420-dev-charlie-support_thead_vector_6_9-v3-10-67cff4271d1d@rivosinc.com> (raw)
In-Reply-To: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com>
From: Heiko Stuebner <heiko@sntech.de>
The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].
Define constants for those to access the elements in a readable way.
Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/include/asm/csr.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 2468c55933cd..13bc99c995d1 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -215,6 +215,11 @@
#define SMSTATEEN0_SSTATEEN0_SHIFT 63
#define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
+/* VCSR flags */
+#define VCSR_VXRM_MASK 3
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXSAT_MASK 1
+
/* symbolic CSR names: */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
--
2.44.0
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>,
Heiko Stuebner <heiko@sntech.de>,
Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v3 10/17] RISC-V: define the elements of the VCSR vector CSR
Date: Sat, 20 Apr 2024 18:04:42 -0700 [thread overview]
Message-ID: <20240420-dev-charlie-support_thead_vector_6_9-v3-10-67cff4271d1d@rivosinc.com> (raw)
In-Reply-To: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com>
From: Heiko Stuebner <heiko@sntech.de>
The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].
Define constants for those to access the elements in a readable way.
Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/include/asm/csr.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 2468c55933cd..13bc99c995d1 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -215,6 +215,11 @@
#define SMSTATEEN0_SSTATEEN0_SHIFT 63
#define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
+/* VCSR flags */
+#define VCSR_VXRM_MASK 3
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXSAT_MASK 1
+
/* symbolic CSR names: */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
--
2.44.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>,
Heiko Stuebner <heiko@sntech.de>,
Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v3 10/17] RISC-V: define the elements of the VCSR vector CSR
Date: Sat, 20 Apr 2024 18:04:42 -0700 [thread overview]
Message-ID: <20240420-dev-charlie-support_thead_vector_6_9-v3-10-67cff4271d1d@rivosinc.com> (raw)
In-Reply-To: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com>
From: Heiko Stuebner <heiko@sntech.de>
The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].
Define constants for those to access the elements in a readable way.
Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/include/asm/csr.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 2468c55933cd..13bc99c995d1 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -215,6 +215,11 @@
#define SMSTATEEN0_SSTATEEN0_SHIFT 63
#define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
+/* VCSR flags */
+#define VCSR_VXRM_MASK 3
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXSAT_MASK 1
+
/* symbolic CSR names: */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
--
2.44.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-04-21 1:05 UTC|newest]
Thread overview: 105+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-21 1:04 [PATCH v3 00/17] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 01/17] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 8:15 ` Guo Ren
2024-04-26 8:15 ` Guo Ren
2024-04-26 8:15 ` Guo Ren
2024-04-21 1:04 ` [PATCH v3 02/17] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 03/17] dt-bindings: riscv: cpus: add a vlen register length property Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 04/17] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 15:17 ` Conor Dooley
2024-04-26 15:17 ` Conor Dooley
2024-04-26 15:17 ` Conor Dooley
2024-04-26 16:21 ` Conor Dooley
2024-04-26 16:21 ` Conor Dooley
2024-04-26 16:21 ` Conor Dooley
2024-04-26 17:03 ` Charlie Jenkins
2024-04-26 17:03 ` Charlie Jenkins
2024-04-26 17:03 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 05/17] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 06/17] riscv: Fix extension subset checking Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-24 14:22 ` Alexandre Ghiti
2024-04-24 14:22 ` Alexandre Ghiti
2024-04-24 14:22 ` Alexandre Ghiti
2024-04-24 14:51 ` Conor Dooley
2024-04-24 14:51 ` Conor Dooley
2024-04-24 14:51 ` Conor Dooley
2024-04-24 15:13 ` Charlie Jenkins
2024-04-24 15:13 ` Charlie Jenkins
2024-04-24 15:13 ` Charlie Jenkins
2024-04-24 15:21 ` Conor Dooley
2024-04-24 15:21 ` Conor Dooley
2024-04-24 15:21 ` Conor Dooley
2024-04-24 15:36 ` Charlie Jenkins
2024-04-24 15:36 ` Charlie Jenkins
2024-04-24 15:36 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 07/17] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 16:00 ` Conor Dooley
2024-04-26 16:00 ` Conor Dooley
2024-04-26 16:00 ` Conor Dooley
2024-04-26 18:00 ` Charlie Jenkins
2024-04-26 18:00 ` Charlie Jenkins
2024-04-26 18:00 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 08/17] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 16:19 ` Conor Dooley
2024-04-26 16:19 ` Conor Dooley
2024-04-26 16:19 ` Conor Dooley
2024-04-26 20:01 ` Charlie Jenkins
2024-04-26 20:01 ` Charlie Jenkins
2024-04-26 20:01 ` Charlie Jenkins
2024-04-26 20:37 ` Conor Dooley
2024-04-26 20:37 ` Conor Dooley
2024-04-26 20:37 ` Conor Dooley
2024-04-21 1:04 ` [PATCH v3 09/17] riscv: drivers: Convert xandespmu to use the vendor extension framework Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 16:25 ` Conor Dooley
2024-04-26 16:25 ` Conor Dooley
2024-04-26 16:25 ` Conor Dooley
2024-04-26 20:34 ` Charlie Jenkins
2024-04-26 20:34 ` Charlie Jenkins
2024-04-26 20:34 ` Charlie Jenkins
2024-04-26 20:46 ` Conor Dooley
2024-04-26 20:46 ` Conor Dooley
2024-04-26 20:46 ` Conor Dooley
2024-04-21 1:04 ` Charlie Jenkins [this message]
2024-04-21 1:04 ` [PATCH v3 10/17] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 11/17] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 12/17] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 13/17] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 14/17] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 15/17] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 16/17] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 17/17] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
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