From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>
Subject: [PATCH v3 02/17] dt-bindings: riscv: Add xtheadvector ISA extension description
Date: Sat, 20 Apr 2024 18:04:34 -0700 [thread overview]
Message-ID: <20240420-dev-charlie-support_thead_vector_6_9-v3-2-67cff4271d1d@rivosinc.com> (raw)
In-Reply-To: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com>
The xtheadvector ISA extension is described on the T-Head extension spec
Github page [1] at commit 95358cb2cca9.
Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc [1]
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 468c646247aa..99d2a9e8c52d 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,6 +477,10 @@ properties:
latency, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ # vendor extensions, each extension sorted alphanumerically under the
+ # vendor they belong to. Vendors are sorted alphanumerically as well.
+
+ # Andes
- const: xandespmu
description:
The Andes Technology performance monitor extension for counter overflow
@@ -484,5 +488,11 @@ properties:
Registers in the AX45MP datasheet.
https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+ # T-HEAD
+ - const: xtheadvector
+ description:
+ The T-HEAD specific 0.7.1 vector implementation as written in
+ https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc.
+
additionalProperties: true
...
--
2.44.0
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>
Subject: [PATCH v3 02/17] dt-bindings: riscv: Add xtheadvector ISA extension description
Date: Sat, 20 Apr 2024 18:04:34 -0700 [thread overview]
Message-ID: <20240420-dev-charlie-support_thead_vector_6_9-v3-2-67cff4271d1d@rivosinc.com> (raw)
In-Reply-To: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com>
The xtheadvector ISA extension is described on the T-Head extension spec
Github page [1] at commit 95358cb2cca9.
Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc [1]
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 468c646247aa..99d2a9e8c52d 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,6 +477,10 @@ properties:
latency, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ # vendor extensions, each extension sorted alphanumerically under the
+ # vendor they belong to. Vendors are sorted alphanumerically as well.
+
+ # Andes
- const: xandespmu
description:
The Andes Technology performance monitor extension for counter overflow
@@ -484,5 +488,11 @@ properties:
Registers in the AX45MP datasheet.
https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+ # T-HEAD
+ - const: xtheadvector
+ description:
+ The T-HEAD specific 0.7.1 vector implementation as written in
+ https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc.
+
additionalProperties: true
...
--
2.44.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>
Subject: [PATCH v3 02/17] dt-bindings: riscv: Add xtheadvector ISA extension description
Date: Sat, 20 Apr 2024 18:04:34 -0700 [thread overview]
Message-ID: <20240420-dev-charlie-support_thead_vector_6_9-v3-2-67cff4271d1d@rivosinc.com> (raw)
In-Reply-To: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com>
The xtheadvector ISA extension is described on the T-Head extension spec
Github page [1] at commit 95358cb2cca9.
Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc [1]
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 468c646247aa..99d2a9e8c52d 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,6 +477,10 @@ properties:
latency, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ # vendor extensions, each extension sorted alphanumerically under the
+ # vendor they belong to. Vendors are sorted alphanumerically as well.
+
+ # Andes
- const: xandespmu
description:
The Andes Technology performance monitor extension for counter overflow
@@ -484,5 +488,11 @@ properties:
Registers in the AX45MP datasheet.
https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+ # T-HEAD
+ - const: xtheadvector
+ description:
+ The T-HEAD specific 0.7.1 vector implementation as written in
+ https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc.
+
additionalProperties: true
...
--
2.44.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-04-21 1:04 UTC|newest]
Thread overview: 105+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-21 1:04 [PATCH v3 00/17] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 01/17] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 8:15 ` Guo Ren
2024-04-26 8:15 ` Guo Ren
2024-04-26 8:15 ` Guo Ren
2024-04-21 1:04 ` Charlie Jenkins [this message]
2024-04-21 1:04 ` [PATCH v3 02/17] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 03/17] dt-bindings: riscv: cpus: add a vlen register length property Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 04/17] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 15:17 ` Conor Dooley
2024-04-26 15:17 ` Conor Dooley
2024-04-26 15:17 ` Conor Dooley
2024-04-26 16:21 ` Conor Dooley
2024-04-26 16:21 ` Conor Dooley
2024-04-26 16:21 ` Conor Dooley
2024-04-26 17:03 ` Charlie Jenkins
2024-04-26 17:03 ` Charlie Jenkins
2024-04-26 17:03 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 05/17] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 06/17] riscv: Fix extension subset checking Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-24 14:22 ` Alexandre Ghiti
2024-04-24 14:22 ` Alexandre Ghiti
2024-04-24 14:22 ` Alexandre Ghiti
2024-04-24 14:51 ` Conor Dooley
2024-04-24 14:51 ` Conor Dooley
2024-04-24 14:51 ` Conor Dooley
2024-04-24 15:13 ` Charlie Jenkins
2024-04-24 15:13 ` Charlie Jenkins
2024-04-24 15:13 ` Charlie Jenkins
2024-04-24 15:21 ` Conor Dooley
2024-04-24 15:21 ` Conor Dooley
2024-04-24 15:21 ` Conor Dooley
2024-04-24 15:36 ` Charlie Jenkins
2024-04-24 15:36 ` Charlie Jenkins
2024-04-24 15:36 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 07/17] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 16:00 ` Conor Dooley
2024-04-26 16:00 ` Conor Dooley
2024-04-26 16:00 ` Conor Dooley
2024-04-26 18:00 ` Charlie Jenkins
2024-04-26 18:00 ` Charlie Jenkins
2024-04-26 18:00 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 08/17] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 16:19 ` Conor Dooley
2024-04-26 16:19 ` Conor Dooley
2024-04-26 16:19 ` Conor Dooley
2024-04-26 20:01 ` Charlie Jenkins
2024-04-26 20:01 ` Charlie Jenkins
2024-04-26 20:01 ` Charlie Jenkins
2024-04-26 20:37 ` Conor Dooley
2024-04-26 20:37 ` Conor Dooley
2024-04-26 20:37 ` Conor Dooley
2024-04-21 1:04 ` [PATCH v3 09/17] riscv: drivers: Convert xandespmu to use the vendor extension framework Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 16:25 ` Conor Dooley
2024-04-26 16:25 ` Conor Dooley
2024-04-26 16:25 ` Conor Dooley
2024-04-26 20:34 ` Charlie Jenkins
2024-04-26 20:34 ` Charlie Jenkins
2024-04-26 20:34 ` Charlie Jenkins
2024-04-26 20:46 ` Conor Dooley
2024-04-26 20:46 ` Conor Dooley
2024-04-26 20:46 ` Conor Dooley
2024-04-21 1:04 ` [PATCH v3 10/17] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 11/17] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 12/17] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 13/17] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 14/17] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 15/17] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 16/17] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 17/17] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
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