From: Conor Dooley <conor@kernel.org>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: "Alexandre Ghiti" <alex@ghiti.fr>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v3 06/17] riscv: Fix extension subset checking
Date: Wed, 24 Apr 2024 16:21:05 +0100 [thread overview]
Message-ID: <20240424-gondola-cosmic-b7a02b2a8619@spud> (raw)
In-Reply-To: <ZikhpEgEoMX/rObu@ghost>
[-- Attachment #1: Type: text/plain, Size: 2358 bytes --]
On Wed, Apr 24, 2024 at 11:13:40AM -0400, Charlie Jenkins wrote:
> On Wed, Apr 24, 2024 at 03:51:54PM +0100, Conor Dooley wrote:
> > On Wed, Apr 24, 2024 at 04:22:02PM +0200, Alexandre Ghiti wrote:
> > > Hi Charlie,
> > >
> > > On 21/04/2024 03:04, Charlie Jenkins wrote:
> > > > This loop is supposed to check if ext->subset_ext_ids[j] is valid, rather
> > > > than if ext->subset_ext_ids[i] is valid, before setting the extension
> > > > id ext->subset_ext_ids[j] in isainfo->isa.
> > > >
> > > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > Fixes: 0d8295ed975b ("riscv: add ISA extension parsing for scalar crypto")
> > > > ---
> > > > arch/riscv/kernel/cpufeature.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > > index 48874aac4871..b537731cadef 100644
> > > > --- a/arch/riscv/kernel/cpufeature.c
> > > > +++ b/arch/riscv/kernel/cpufeature.c
> > > > @@ -609,7 +609,7 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
> > > > if (ext->subset_ext_size) {
> > > > for (int j = 0; j < ext->subset_ext_size; j++) {
> > > > - if (riscv_isa_extension_check(ext->subset_ext_ids[i]))
> > > > + if (riscv_isa_extension_check(ext->subset_ext_ids[j]))
> > > > set_bit(ext->subset_ext_ids[j], isainfo->isa);
> > > > }
> > > > }
> > > >
> > >
> > > I think this should go into -fixes, let's check with Palmer if he wants to
> > > take this patch only or if you should send the patch on its own.
> >
> > I think splitting out this and patch 1 into a new series targeting fixes
> > would probably make things clearer?
>
> Okay I can do that. I will give it a bit more time before I send this
> series split into two to allow time for the rest of the patches to
> gather comments so I avoid sending too many duplicate patches.
Ye, I do hope to get back to this series later in the week when I have
time to actually read through all of the patches in detail.
However, you wouldn't have to resend both parts of the series - you can
just split out the fixes portion and send that, leaving the rest of the
series sitting on the list to gather comments.
[-- Attachment #2: signature.asc --]
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: "Alexandre Ghiti" <alex@ghiti.fr>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v3 06/17] riscv: Fix extension subset checking
Date: Wed, 24 Apr 2024 16:21:05 +0100 [thread overview]
Message-ID: <20240424-gondola-cosmic-b7a02b2a8619@spud> (raw)
In-Reply-To: <ZikhpEgEoMX/rObu@ghost>
[-- Attachment #1.1: Type: text/plain, Size: 2358 bytes --]
On Wed, Apr 24, 2024 at 11:13:40AM -0400, Charlie Jenkins wrote:
> On Wed, Apr 24, 2024 at 03:51:54PM +0100, Conor Dooley wrote:
> > On Wed, Apr 24, 2024 at 04:22:02PM +0200, Alexandre Ghiti wrote:
> > > Hi Charlie,
> > >
> > > On 21/04/2024 03:04, Charlie Jenkins wrote:
> > > > This loop is supposed to check if ext->subset_ext_ids[j] is valid, rather
> > > > than if ext->subset_ext_ids[i] is valid, before setting the extension
> > > > id ext->subset_ext_ids[j] in isainfo->isa.
> > > >
> > > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > Fixes: 0d8295ed975b ("riscv: add ISA extension parsing for scalar crypto")
> > > > ---
> > > > arch/riscv/kernel/cpufeature.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > > index 48874aac4871..b537731cadef 100644
> > > > --- a/arch/riscv/kernel/cpufeature.c
> > > > +++ b/arch/riscv/kernel/cpufeature.c
> > > > @@ -609,7 +609,7 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
> > > > if (ext->subset_ext_size) {
> > > > for (int j = 0; j < ext->subset_ext_size; j++) {
> > > > - if (riscv_isa_extension_check(ext->subset_ext_ids[i]))
> > > > + if (riscv_isa_extension_check(ext->subset_ext_ids[j]))
> > > > set_bit(ext->subset_ext_ids[j], isainfo->isa);
> > > > }
> > > > }
> > > >
> > >
> > > I think this should go into -fixes, let's check with Palmer if he wants to
> > > take this patch only or if you should send the patch on its own.
> >
> > I think splitting out this and patch 1 into a new series targeting fixes
> > would probably make things clearer?
>
> Okay I can do that. I will give it a bit more time before I send this
> series split into two to allow time for the rest of the patches to
> gather comments so I avoid sending too many duplicate patches.
Ye, I do hope to get back to this series later in the week when I have
time to actually read through all of the patches in detail.
However, you wouldn't have to resend both parts of the series - you can
just split out the fixes portion and send that, leaving the rest of the
series sitting on the list to gather comments.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: "Alexandre Ghiti" <alex@ghiti.fr>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v3 06/17] riscv: Fix extension subset checking
Date: Wed, 24 Apr 2024 16:21:05 +0100 [thread overview]
Message-ID: <20240424-gondola-cosmic-b7a02b2a8619@spud> (raw)
In-Reply-To: <ZikhpEgEoMX/rObu@ghost>
[-- Attachment #1.1: Type: text/plain, Size: 2358 bytes --]
On Wed, Apr 24, 2024 at 11:13:40AM -0400, Charlie Jenkins wrote:
> On Wed, Apr 24, 2024 at 03:51:54PM +0100, Conor Dooley wrote:
> > On Wed, Apr 24, 2024 at 04:22:02PM +0200, Alexandre Ghiti wrote:
> > > Hi Charlie,
> > >
> > > On 21/04/2024 03:04, Charlie Jenkins wrote:
> > > > This loop is supposed to check if ext->subset_ext_ids[j] is valid, rather
> > > > than if ext->subset_ext_ids[i] is valid, before setting the extension
> > > > id ext->subset_ext_ids[j] in isainfo->isa.
> > > >
> > > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > Fixes: 0d8295ed975b ("riscv: add ISA extension parsing for scalar crypto")
> > > > ---
> > > > arch/riscv/kernel/cpufeature.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > > index 48874aac4871..b537731cadef 100644
> > > > --- a/arch/riscv/kernel/cpufeature.c
> > > > +++ b/arch/riscv/kernel/cpufeature.c
> > > > @@ -609,7 +609,7 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
> > > > if (ext->subset_ext_size) {
> > > > for (int j = 0; j < ext->subset_ext_size; j++) {
> > > > - if (riscv_isa_extension_check(ext->subset_ext_ids[i]))
> > > > + if (riscv_isa_extension_check(ext->subset_ext_ids[j]))
> > > > set_bit(ext->subset_ext_ids[j], isainfo->isa);
> > > > }
> > > > }
> > > >
> > >
> > > I think this should go into -fixes, let's check with Palmer if he wants to
> > > take this patch only or if you should send the patch on its own.
> >
> > I think splitting out this and patch 1 into a new series targeting fixes
> > would probably make things clearer?
>
> Okay I can do that. I will give it a bit more time before I send this
> series split into two to allow time for the rest of the patches to
> gather comments so I avoid sending too many duplicate patches.
Ye, I do hope to get back to this series later in the week when I have
time to actually read through all of the patches in detail.
However, you wouldn't have to resend both parts of the series - you can
just split out the fixes portion and send that, leaving the rest of the
series sitting on the list to gather comments.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
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next prev parent reply other threads:[~2024-04-24 15:21 UTC|newest]
Thread overview: 105+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-21 1:04 [PATCH v3 00/17] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 01/17] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 8:15 ` Guo Ren
2024-04-26 8:15 ` Guo Ren
2024-04-26 8:15 ` Guo Ren
2024-04-21 1:04 ` [PATCH v3 02/17] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 03/17] dt-bindings: riscv: cpus: add a vlen register length property Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 04/17] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 15:17 ` Conor Dooley
2024-04-26 15:17 ` Conor Dooley
2024-04-26 15:17 ` Conor Dooley
2024-04-26 16:21 ` Conor Dooley
2024-04-26 16:21 ` Conor Dooley
2024-04-26 16:21 ` Conor Dooley
2024-04-26 17:03 ` Charlie Jenkins
2024-04-26 17:03 ` Charlie Jenkins
2024-04-26 17:03 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 05/17] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 06/17] riscv: Fix extension subset checking Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-24 14:22 ` Alexandre Ghiti
2024-04-24 14:22 ` Alexandre Ghiti
2024-04-24 14:22 ` Alexandre Ghiti
2024-04-24 14:51 ` Conor Dooley
2024-04-24 14:51 ` Conor Dooley
2024-04-24 14:51 ` Conor Dooley
2024-04-24 15:13 ` Charlie Jenkins
2024-04-24 15:13 ` Charlie Jenkins
2024-04-24 15:13 ` Charlie Jenkins
2024-04-24 15:21 ` Conor Dooley [this message]
2024-04-24 15:21 ` Conor Dooley
2024-04-24 15:21 ` Conor Dooley
2024-04-24 15:36 ` Charlie Jenkins
2024-04-24 15:36 ` Charlie Jenkins
2024-04-24 15:36 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 07/17] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 16:00 ` Conor Dooley
2024-04-26 16:00 ` Conor Dooley
2024-04-26 16:00 ` Conor Dooley
2024-04-26 18:00 ` Charlie Jenkins
2024-04-26 18:00 ` Charlie Jenkins
2024-04-26 18:00 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 08/17] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 16:19 ` Conor Dooley
2024-04-26 16:19 ` Conor Dooley
2024-04-26 16:19 ` Conor Dooley
2024-04-26 20:01 ` Charlie Jenkins
2024-04-26 20:01 ` Charlie Jenkins
2024-04-26 20:01 ` Charlie Jenkins
2024-04-26 20:37 ` Conor Dooley
2024-04-26 20:37 ` Conor Dooley
2024-04-26 20:37 ` Conor Dooley
2024-04-21 1:04 ` [PATCH v3 09/17] riscv: drivers: Convert xandespmu to use the vendor extension framework Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-26 16:25 ` Conor Dooley
2024-04-26 16:25 ` Conor Dooley
2024-04-26 16:25 ` Conor Dooley
2024-04-26 20:34 ` Charlie Jenkins
2024-04-26 20:34 ` Charlie Jenkins
2024-04-26 20:34 ` Charlie Jenkins
2024-04-26 20:46 ` Conor Dooley
2024-04-26 20:46 ` Conor Dooley
2024-04-26 20:46 ` Conor Dooley
2024-04-21 1:04 ` [PATCH v3 10/17] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 11/17] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 12/17] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 13/17] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 14/17] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 15/17] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 16/17] selftests: riscv: Fix vector tests Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` [PATCH v3 17/17] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
2024-04-21 1:04 ` Charlie Jenkins
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