From: Markos Chandras <markos.chandras@imgtec.com> To: <linux-mips@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Subject: [PATCH 18/19] MIPS: kernel: cpu-probe: Fix VTLB/FTLB configuration for R6 Date: Thu, 9 Jul 2015 10:40:52 +0100 [thread overview] Message-ID: <1436434853-30001-19-git-send-email-markos.chandras@imgtec.com> (raw) In-Reply-To: <1436434853-30001-1-git-send-email-markos.chandras@imgtec.com> R6 has dropped the MMUExtDef field from the config4 register and it now returns 0. However, the return value means nothing in that case and the only supported configuration for R6 is the VTLB+FTLB (MMUextDef == 3). As a result, rework the code so that the correct value is set for R6 cores. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/kernel/cpu-probe.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 6da5f2db6792..62dae429fe70 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -546,7 +546,16 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c) if (cpu_has_tlb) { if (((config4 & MIPS_CONF4_IE) >> 29) == 2) c->options |= MIPS_CPU_TLBINV; - mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; + /* + * This is a bit ugly. R6 has dropped that field from + * config4 and the only valid configuration is VTLB+FTLB so + * set a good value for mmuextdef for that case. + */ + if (cpu_has_mips_r6) + mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; + else + mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; + switch (mmuextdef) { case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; -- 2.4.5
WARNING: multiple messages have this Message-ID (diff)
From: Markos Chandras <markos.chandras@imgtec.com> To: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Subject: [PATCH 18/19] MIPS: kernel: cpu-probe: Fix VTLB/FTLB configuration for R6 Date: Thu, 9 Jul 2015 10:40:52 +0100 [thread overview] Message-ID: <1436434853-30001-19-git-send-email-markos.chandras@imgtec.com> (raw) Message-ID: <20150709094052.ioEMFSauAGZ7E2mVOA_jFEhlbvl_K5hTWauD7bRQBwI@z> (raw) In-Reply-To: <1436434853-30001-1-git-send-email-markos.chandras@imgtec.com> R6 has dropped the MMUExtDef field from the config4 register and it now returns 0. However, the return value means nothing in that case and the only supported configuration for R6 is the VTLB+FTLB (MMUextDef == 3). As a result, rework the code so that the correct value is set for R6 cores. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/kernel/cpu-probe.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 6da5f2db6792..62dae429fe70 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -546,7 +546,16 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c) if (cpu_has_tlb) { if (((config4 & MIPS_CONF4_IE) >> 29) == 2) c->options |= MIPS_CPU_TLBINV; - mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; + /* + * This is a bit ugly. R6 has dropped that field from + * config4 and the only valid configuration is VTLB+FTLB so + * set a good value for mmuextdef for that case. + */ + if (cpu_has_mips_r6) + mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; + else + mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; + switch (mmuextdef) { case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; -- 2.4.5
next prev parent reply other threads:[~2015-07-09 9:46 UTC|newest] Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-07-09 9:40 [PATCH 00/19] Initial I6400 and CM3 support Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 01/19] MIPS: Add MIPS I6400 PRid and cputype identifiers Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 02/19] MIPS: Add cases for CPU_I6400 Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 10:03 ` Ralf Baechle 2015-07-09 10:14 ` Markos Chandras 2015-07-09 10:14 ` Markos Chandras 2015-07-09 11:43 ` Ralf Baechle 2015-07-09 9:40 ` [PATCH 03/19] MIPS: Add MIPS I6400 probe support Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 04/19] MIPS: Kconfig: Disable MIPS MT and SMP implementations for R6 Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 05/19] MIPS: asm: mips-cm: Implement mips_cm_revision Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 11:09 ` Sergei Shtylyov 2015-07-09 16:05 ` Markos Chandras 2015-07-09 16:05 ` Markos Chandras 2015-07-09 11:29 ` James Hogan 2015-07-09 11:29 ` James Hogan 2015-07-09 16:05 ` Markos Chandras 2015-07-09 16:05 ` Markos Chandras 2015-07-10 9:12 ` [PATCH v2 " Markos Chandras 2015-07-10 9:12 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 06/19] MIPS: asm: add CM GCR_L2_CONFIG register accessors Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 07/19] MIPS: mm: c-r4k: extend way_string array Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 08/19] MIPS: support CM3 L2 cache Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 09/19] MIPS: Add platform callback before initializing the " Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 10/19] MIPS: asm: mips-cm: Extend CM accessors for 64-bit CPUs Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-14 8:14 ` [PATCH v2 " Markos Chandras 2015-07-14 8:14 ` Markos Chandras 2015-07-14 8:30 ` Paul Burton 2015-07-14 8:30 ` Paul Burton 2015-07-14 8:35 ` Paul Burton 2015-07-14 8:35 ` Paul Burton 2015-07-14 8:45 ` Markos Chandras 2015-07-14 8:45 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 11/19] MIPS: kernel: mips-cm: The CMGCRBase register is 64-bit on MIPS64 Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 12/19] MIPS: kernel: mips-cpc: Fix type for GCR CPC base reg for 64-bit Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 13/19] MIPS: kernel: mips-cm: Add support for reporting CM cache errors Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 14/19] drivers: irqchip: irq-mips-gic: Extend GIC accessors for 64-bit CMs Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-14 9:26 ` [PATCH v2 " Markos Chandras 2015-07-14 9:26 ` Markos Chandras 2015-07-14 11:57 ` Jonas Gorski 2015-07-14 12:21 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 15/19] drivers: irqchip: irq-mips-gic: Add support for CM3 64-bit timer irqs Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 16/19] MIPS: kernel: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 17/19] MIPS: Add default case for the FTLB enable/disable code Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` Markos Chandras [this message] 2015-07-09 9:40 ` [PATCH 18/19] MIPS: kernel: cpu-probe: Fix VTLB/FTLB configuration for R6 Markos Chandras 2015-07-09 9:40 ` [PATCH 19/19] MIPS: Set up FTLB probability for I6400 Markos Chandras 2015-07-09 9:40 ` Markos Chandras
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