From: Markos Chandras <markos.chandras@imgtec.com> To: <linux-mips@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com>, Markos Chandras <markos.chandras@imgtec.com> Subject: [PATCH 08/19] MIPS: support CM3 L2 cache Date: Thu, 9 Jul 2015 10:40:42 +0100 [thread overview] Message-ID: <1436434853-30001-9-git-send-email-markos.chandras@imgtec.com> (raw) In-Reply-To: <1436434853-30001-1-git-send-email-markos.chandras@imgtec.com> From: Paul Burton <paul.burton@imgtec.com> Detect the L2 cache configuration from GCR_L2_CONFIG when a CM3 is present in the system, rather than from Config2 which does not expose the L2 configuration on I6400. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/mm/sc-mips.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 4ceafd13870c..5fa452e8cff9 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -14,6 +14,7 @@ #include <asm/pgtable.h> #include <asm/mmu_context.h> #include <asm/r4kcache.h> +#include <asm/mips-cm.h> /* * MIPS32/MIPS64 L2 cache handling @@ -94,6 +95,34 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) return 1; } +static int __init mips_sc_probe_cm3(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned long cfg = read_gcr_l2_config(); + unsigned long sets, line_sz, assoc; + + if (cfg & CM_GCR_L2_CONFIG_BYPASS_MSK) + return 0; + + sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE_MSK; + sets >>= CM_GCR_L2_CONFIG_SET_SIZE_SHF; + c->scache.sets = 64 << sets; + + line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK; + line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF; + c->scache.linesz = 2 << line_sz; + + assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK; + assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF; + c->scache.ways = assoc + 1; + c->scache.waysize = c->scache.sets * c->scache.linesz; + c->scache.waybit = __ffs(c->scache.waysize); + + c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; + + return 1; +} + static inline int __init mips_sc_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -103,6 +132,9 @@ static inline int __init mips_sc_probe(void) /* Mark as not present until probe completed */ c->scache.flags |= MIPS_CACHE_NOT_PRESENT; + if (mips_cm_revision() >= CM_REV_CM3) + return mips_sc_probe_cm3(); + /* Ignore anything but MIPSxx processors */ if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | -- 2.4.5
WARNING: multiple messages have this Message-ID (diff)
From: Markos Chandras <markos.chandras@imgtec.com> To: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com>, Markos Chandras <markos.chandras@imgtec.com> Subject: [PATCH 08/19] MIPS: support CM3 L2 cache Date: Thu, 9 Jul 2015 10:40:42 +0100 [thread overview] Message-ID: <1436434853-30001-9-git-send-email-markos.chandras@imgtec.com> (raw) Message-ID: <20150709094042.nrxYrw_Tm96Wtvv3XJqEa9SaesRFigaiZ0WTWT6aYZY@z> (raw) In-Reply-To: <1436434853-30001-1-git-send-email-markos.chandras@imgtec.com> From: Paul Burton <paul.burton@imgtec.com> Detect the L2 cache configuration from GCR_L2_CONFIG when a CM3 is present in the system, rather than from Config2 which does not expose the L2 configuration on I6400. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/mm/sc-mips.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 4ceafd13870c..5fa452e8cff9 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -14,6 +14,7 @@ #include <asm/pgtable.h> #include <asm/mmu_context.h> #include <asm/r4kcache.h> +#include <asm/mips-cm.h> /* * MIPS32/MIPS64 L2 cache handling @@ -94,6 +95,34 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) return 1; } +static int __init mips_sc_probe_cm3(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned long cfg = read_gcr_l2_config(); + unsigned long sets, line_sz, assoc; + + if (cfg & CM_GCR_L2_CONFIG_BYPASS_MSK) + return 0; + + sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE_MSK; + sets >>= CM_GCR_L2_CONFIG_SET_SIZE_SHF; + c->scache.sets = 64 << sets; + + line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK; + line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF; + c->scache.linesz = 2 << line_sz; + + assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK; + assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF; + c->scache.ways = assoc + 1; + c->scache.waysize = c->scache.sets * c->scache.linesz; + c->scache.waybit = __ffs(c->scache.waysize); + + c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; + + return 1; +} + static inline int __init mips_sc_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -103,6 +132,9 @@ static inline int __init mips_sc_probe(void) /* Mark as not present until probe completed */ c->scache.flags |= MIPS_CACHE_NOT_PRESENT; + if (mips_cm_revision() >= CM_REV_CM3) + return mips_sc_probe_cm3(); + /* Ignore anything but MIPSxx processors */ if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | -- 2.4.5
next prev parent reply other threads:[~2015-07-09 9:43 UTC|newest] Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-07-09 9:40 [PATCH 00/19] Initial I6400 and CM3 support Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 01/19] MIPS: Add MIPS I6400 PRid and cputype identifiers Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 02/19] MIPS: Add cases for CPU_I6400 Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 10:03 ` Ralf Baechle 2015-07-09 10:14 ` Markos Chandras 2015-07-09 10:14 ` Markos Chandras 2015-07-09 11:43 ` Ralf Baechle 2015-07-09 9:40 ` [PATCH 03/19] MIPS: Add MIPS I6400 probe support Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 04/19] MIPS: Kconfig: Disable MIPS MT and SMP implementations for R6 Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 05/19] MIPS: asm: mips-cm: Implement mips_cm_revision Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 11:09 ` Sergei Shtylyov 2015-07-09 16:05 ` Markos Chandras 2015-07-09 16:05 ` Markos Chandras 2015-07-09 11:29 ` James Hogan 2015-07-09 11:29 ` James Hogan 2015-07-09 16:05 ` Markos Chandras 2015-07-09 16:05 ` Markos Chandras 2015-07-10 9:12 ` [PATCH v2 " Markos Chandras 2015-07-10 9:12 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 06/19] MIPS: asm: add CM GCR_L2_CONFIG register accessors Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 07/19] MIPS: mm: c-r4k: extend way_string array Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` Markos Chandras [this message] 2015-07-09 9:40 ` [PATCH 08/19] MIPS: support CM3 L2 cache Markos Chandras 2015-07-09 9:40 ` [PATCH 09/19] MIPS: Add platform callback before initializing the " Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 10/19] MIPS: asm: mips-cm: Extend CM accessors for 64-bit CPUs Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-14 8:14 ` [PATCH v2 " Markos Chandras 2015-07-14 8:14 ` Markos Chandras 2015-07-14 8:30 ` Paul Burton 2015-07-14 8:30 ` Paul Burton 2015-07-14 8:35 ` Paul Burton 2015-07-14 8:35 ` Paul Burton 2015-07-14 8:45 ` Markos Chandras 2015-07-14 8:45 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 11/19] MIPS: kernel: mips-cm: The CMGCRBase register is 64-bit on MIPS64 Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 12/19] MIPS: kernel: mips-cpc: Fix type for GCR CPC base reg for 64-bit Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 13/19] MIPS: kernel: mips-cm: Add support for reporting CM cache errors Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 14/19] drivers: irqchip: irq-mips-gic: Extend GIC accessors for 64-bit CMs Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-14 9:26 ` [PATCH v2 " Markos Chandras 2015-07-14 9:26 ` Markos Chandras 2015-07-14 11:57 ` Jonas Gorski 2015-07-14 12:21 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 15/19] drivers: irqchip: irq-mips-gic: Add support for CM3 64-bit timer irqs Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 16/19] MIPS: kernel: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 17/19] MIPS: Add default case for the FTLB enable/disable code Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 18/19] MIPS: kernel: cpu-probe: Fix VTLB/FTLB configuration for R6 Markos Chandras 2015-07-09 9:40 ` Markos Chandras 2015-07-09 9:40 ` [PATCH 19/19] MIPS: Set up FTLB probability for I6400 Markos Chandras 2015-07-09 9:40 ` Markos Chandras
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