[PATCH 07/19] MIPS: mm: c-r4k: extend way_string array

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From: Markos Chandras <markos.chandras@imgtec.com>
To: <linux-mips@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>,
	Markos Chandras <markos.chandras@imgtec.com>
Subject: [PATCH 07/19] MIPS: mm: c-r4k: extend way_string array
Date: Thu, 9 Jul 2015 10:40:41 +0100	[thread overview]
Message-ID: <1436434853-30001-8-git-send-email-markos.chandras@imgtec.com> (raw)
In-Reply-To: <1436434853-30001-1-git-send-email-markos.chandras@imgtec.com>

From: Paul Burton <paul.burton@imgtec.com>

The L2 cache in the I6400 core has 16 ways, so extend the way_string
array to take such caches into account.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/mm/c-r4k.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index c3e777fc5e8b..a9867c3222b1 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -937,7 +937,9 @@ static void b5k_instruction_hazard(void)
 }
 
 static char *way_string[] = { NULL, "direct mapped", "2-way",
-	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
+	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
+	"9-way", "10-way", "11-way", "12-way",
+	"13-way", "14-way", "15-way", "16-way",
 };
 
 static void probe_pcache(void)
-- 
2.4.5

WARNING: multiple messages have this Message-ID (diff)

From: Markos Chandras <markos.chandras@imgtec.com>
To: linux-mips@linux-mips.org
Cc: Paul Burton <paul.burton@imgtec.com>,
	Markos Chandras <markos.chandras@imgtec.com>
Subject: [PATCH 07/19] MIPS: mm: c-r4k: extend way_string array
Date: Thu, 9 Jul 2015 10:40:41 +0100	[thread overview]
Message-ID: <1436434853-30001-8-git-send-email-markos.chandras@imgtec.com> (raw)
Message-ID: <20150709094041.FsVkv-asFFDNCeQDsfyJl-IBw8Pt-XMdfqZyxC2FTSU@z> (raw)
In-Reply-To: <1436434853-30001-1-git-send-email-markos.chandras@imgtec.com>

From: Paul Burton <paul.burton@imgtec.com>

The L2 cache in the I6400 core has 16 ways, so extend the way_string
array to take such caches into account.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
 arch/mips/mm/c-r4k.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index c3e777fc5e8b..a9867c3222b1 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -937,7 +937,9 @@ static void b5k_instruction_hazard(void)
 }
 
 static char *way_string[] = { NULL, "direct mapped", "2-way",
-	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
+	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
+	"9-way", "10-way", "11-way", "12-way",
+	"13-way", "14-way", "15-way", "16-way",
 };
 
 static void probe_pcache(void)
-- 
2.4.5

next prev parent reply	other threads:[~2015-07-09  9:43 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-09  9:40 [PATCH 00/19] Initial I6400 and CM3 support Markos Chandras
2015-07-09  9:40 ` Markos Chandras
2015-07-09  9:40 ` [PATCH 01/19] MIPS: Add MIPS I6400 PRid and cputype identifiers Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 02/19] MIPS: Add cases for CPU_I6400 Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09 10:03   ` Ralf Baechle
2015-07-09 10:14     ` Markos Chandras
2015-07-09 10:14       ` Markos Chandras
2015-07-09 11:43       ` Ralf Baechle
2015-07-09  9:40 ` [PATCH 03/19] MIPS: Add MIPS I6400 probe support Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 04/19] MIPS: Kconfig: Disable MIPS MT and SMP implementations for R6 Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 05/19] MIPS: asm: mips-cm: Implement mips_cm_revision Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09 11:09   ` Sergei Shtylyov
2015-07-09 16:05     ` Markos Chandras
2015-07-09 16:05       ` Markos Chandras
2015-07-09 11:29   ` James Hogan
2015-07-09 11:29     ` James Hogan
2015-07-09 16:05     ` Markos Chandras
2015-07-09 16:05       ` Markos Chandras
2015-07-10  9:12   ` [PATCH v2 " Markos Chandras
2015-07-10  9:12     ` Markos Chandras
2015-07-09  9:40 ` [PATCH 06/19] MIPS: asm: add CM GCR_L2_CONFIG register accessors Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` Markos Chandras [this message]
2015-07-09  9:40   ` [PATCH 07/19] MIPS: mm: c-r4k: extend way_string array Markos Chandras
2015-07-09  9:40 ` [PATCH 08/19] MIPS: support CM3 L2 cache Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 09/19] MIPS: Add platform callback before initializing the " Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 10/19] MIPS: asm: mips-cm: Extend CM accessors for 64-bit CPUs Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-14  8:14   ` [PATCH v2 " Markos Chandras
2015-07-14  8:14     ` Markos Chandras
2015-07-14  8:30     ` Paul Burton
2015-07-14  8:30       ` Paul Burton
2015-07-14  8:35       ` Paul Burton
2015-07-14  8:35         ` Paul Burton
2015-07-14  8:45         ` Markos Chandras
2015-07-14  8:45           ` Markos Chandras
2015-07-09  9:40 ` [PATCH 11/19] MIPS: kernel: mips-cm: The CMGCRBase register is 64-bit on MIPS64 Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 12/19] MIPS: kernel: mips-cpc: Fix type for GCR CPC base reg for 64-bit Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 13/19] MIPS: kernel: mips-cm: Add support for reporting CM cache errors Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 14/19] drivers: irqchip: irq-mips-gic: Extend GIC accessors for 64-bit CMs Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-14  9:26   ` [PATCH v2 " Markos Chandras
2015-07-14  9:26     ` Markos Chandras
2015-07-14 11:57     ` Jonas Gorski
2015-07-14 12:21       ` Markos Chandras
2015-07-09  9:40 ` [PATCH 15/19] drivers: irqchip: irq-mips-gic: Add support for CM3 64-bit timer irqs Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 16/19] MIPS: kernel: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 17/19] MIPS: Add default case for the FTLB enable/disable code Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 18/19] MIPS: kernel: cpu-probe: Fix VTLB/FTLB configuration for R6 Markos Chandras
2015-07-09  9:40   ` Markos Chandras
2015-07-09  9:40 ` [PATCH 19/19] MIPS: Set up FTLB probability for I6400 Markos Chandras
2015-07-09  9:40   ` Markos Chandras

find likely ancestor, descendant, or conflicting patches for this message:
dfblob:c3e777fc5e8 dfblob:c3e777fc5e8 dfblob:a9867c3222b
dfblob:a9867c3222b
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