From: Markos Chandras <Markos.Chandras@imgtec.com>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>,
<linux-mips@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Subject: Re: [PATCH 05/19] MIPS: asm: mips-cm: Implement mips_cm_revision
Date: Thu, 9 Jul 2015 17:05:29 +0100 [thread overview]
Message-ID: <559E9BC9.5050700@imgtec.com> (raw)
In-Reply-To: <559E5662.3010800@cogentembedded.com>
On 07/09/2015 12:09 PM, Sergei Shtylyov wrote:
> On 7/9/2015 12:40 PM, Markos Chandras wrote:
>
>> From: Paul Burton <paul.burton@imgtec.com>
>
>> Provide a function to trivially return the version of the CM present in
>> the system, or 0 if no CM is present. The mips_cm_revision() will be
>> used later on to determine the CM register width, so it must not use
>> the regular CM accessors to read the revision register since that will
>> lead to build failures due to recursive inlines.
>
>> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>> ---
>> arch/mips/include/asm/mips-cm.h | 29 +++++++++++++++++++++++++++++
>> 1 file changed, 29 insertions(+)
>
>> diff --git a/arch/mips/include/asm/mips-cm.h
>> b/arch/mips/include/asm/mips-cm.h
>> index edc7ee95269e..29ff74a629f6 100644
>> --- a/arch/mips/include/asm/mips-cm.h
>> +++ b/arch/mips/include/asm/mips-cm.h
>> @@ -189,6 +189,13 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
>> #define CM_GCR_REV_MINOR_SHF 0
>> #define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0)
>>
>> +#define CM_ENCODE_REV(major, minor) \
>> + ((major << CM_GCR_REV_MAJOR_SHF) | \
>> + ((minor) << CM_GCR_REV_MINOR_SHF))
>
> Enclosing 'minor' into parens and not enclosing 'major' doesn't look
> very consistent... :-)
Ok I will fix it
>
> [...]
>> @@ -324,4 +331,26 @@ static inline int mips_cm_l2sync(void)
>> return 0;
>> }
>>
>> +/**
>> + * mips_cm_revision - return CM revision
>> + *
>> + * Returns the revision of the CM, from GCR_REV, or 0 if no CM is
>> present.
>> + * The return value should be checked against the CM_REV_* macros.
>> + */
>> +static inline int mips_cm_revision(void)
>> +{
>> + static int mips_cm_revision_nr = -1;
>
> Won't this variable be allocated per source file (including this
> header)?
I will drop the static variable since the implementation changed
overtime and there is no need to call mips_cm_revision() so often anymore.
--
markos
WARNING: multiple messages have this Message-ID (diff)
From: Markos Chandras <Markos.Chandras@imgtec.com>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>,
linux-mips@linux-mips.org
Cc: Paul Burton <paul.burton@imgtec.com>
Subject: Re: [PATCH 05/19] MIPS: asm: mips-cm: Implement mips_cm_revision
Date: Thu, 9 Jul 2015 17:05:29 +0100 [thread overview]
Message-ID: <559E9BC9.5050700@imgtec.com> (raw)
Message-ID: <20150709160529.3uKwuxz3d5gl9t7_dlB9nLWJAh7Lw71FU4tK7EJJuWE@z> (raw)
In-Reply-To: <559E5662.3010800@cogentembedded.com>
On 07/09/2015 12:09 PM, Sergei Shtylyov wrote:
> On 7/9/2015 12:40 PM, Markos Chandras wrote:
>
>> From: Paul Burton <paul.burton@imgtec.com>
>
>> Provide a function to trivially return the version of the CM present in
>> the system, or 0 if no CM is present. The mips_cm_revision() will be
>> used later on to determine the CM register width, so it must not use
>> the regular CM accessors to read the revision register since that will
>> lead to build failures due to recursive inlines.
>
>> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>> ---
>> arch/mips/include/asm/mips-cm.h | 29 +++++++++++++++++++++++++++++
>> 1 file changed, 29 insertions(+)
>
>> diff --git a/arch/mips/include/asm/mips-cm.h
>> b/arch/mips/include/asm/mips-cm.h
>> index edc7ee95269e..29ff74a629f6 100644
>> --- a/arch/mips/include/asm/mips-cm.h
>> +++ b/arch/mips/include/asm/mips-cm.h
>> @@ -189,6 +189,13 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
>> #define CM_GCR_REV_MINOR_SHF 0
>> #define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0)
>>
>> +#define CM_ENCODE_REV(major, minor) \
>> + ((major << CM_GCR_REV_MAJOR_SHF) | \
>> + ((minor) << CM_GCR_REV_MINOR_SHF))
>
> Enclosing 'minor' into parens and not enclosing 'major' doesn't look
> very consistent... :-)
Ok I will fix it
>
> [...]
>> @@ -324,4 +331,26 @@ static inline int mips_cm_l2sync(void)
>> return 0;
>> }
>>
>> +/**
>> + * mips_cm_revision - return CM revision
>> + *
>> + * Returns the revision of the CM, from GCR_REV, or 0 if no CM is
>> present.
>> + * The return value should be checked against the CM_REV_* macros.
>> + */
>> +static inline int mips_cm_revision(void)
>> +{
>> + static int mips_cm_revision_nr = -1;
>
> Won't this variable be allocated per source file (including this
> header)?
I will drop the static variable since the implementation changed
overtime and there is no need to call mips_cm_revision() so often anymore.
--
markos
next prev parent reply other threads:[~2015-07-09 16:05 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-09 9:40 [PATCH 00/19] Initial I6400 and CM3 support Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 01/19] MIPS: Add MIPS I6400 PRid and cputype identifiers Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 02/19] MIPS: Add cases for CPU_I6400 Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 10:03 ` Ralf Baechle
2015-07-09 10:14 ` Markos Chandras
2015-07-09 10:14 ` Markos Chandras
2015-07-09 11:43 ` Ralf Baechle
2015-07-09 9:40 ` [PATCH 03/19] MIPS: Add MIPS I6400 probe support Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 04/19] MIPS: Kconfig: Disable MIPS MT and SMP implementations for R6 Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 05/19] MIPS: asm: mips-cm: Implement mips_cm_revision Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 11:09 ` Sergei Shtylyov
2015-07-09 16:05 ` Markos Chandras [this message]
2015-07-09 16:05 ` Markos Chandras
2015-07-09 11:29 ` James Hogan
2015-07-09 11:29 ` James Hogan
2015-07-09 16:05 ` Markos Chandras
2015-07-09 16:05 ` Markos Chandras
2015-07-10 9:12 ` [PATCH v2 " Markos Chandras
2015-07-10 9:12 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 06/19] MIPS: asm: add CM GCR_L2_CONFIG register accessors Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 07/19] MIPS: mm: c-r4k: extend way_string array Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 08/19] MIPS: support CM3 L2 cache Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 09/19] MIPS: Add platform callback before initializing the " Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 10/19] MIPS: asm: mips-cm: Extend CM accessors for 64-bit CPUs Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-14 8:14 ` [PATCH v2 " Markos Chandras
2015-07-14 8:14 ` Markos Chandras
2015-07-14 8:30 ` Paul Burton
2015-07-14 8:30 ` Paul Burton
2015-07-14 8:35 ` Paul Burton
2015-07-14 8:35 ` Paul Burton
2015-07-14 8:45 ` Markos Chandras
2015-07-14 8:45 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 11/19] MIPS: kernel: mips-cm: The CMGCRBase register is 64-bit on MIPS64 Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 12/19] MIPS: kernel: mips-cpc: Fix type for GCR CPC base reg for 64-bit Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 13/19] MIPS: kernel: mips-cm: Add support for reporting CM cache errors Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 14/19] drivers: irqchip: irq-mips-gic: Extend GIC accessors for 64-bit CMs Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-14 9:26 ` [PATCH v2 " Markos Chandras
2015-07-14 9:26 ` Markos Chandras
2015-07-14 11:57 ` Jonas Gorski
2015-07-14 12:21 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 15/19] drivers: irqchip: irq-mips-gic: Add support for CM3 64-bit timer irqs Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 16/19] MIPS: kernel: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 17/19] MIPS: Add default case for the FTLB enable/disable code Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 18/19] MIPS: kernel: cpu-probe: Fix VTLB/FTLB configuration for R6 Markos Chandras
2015-07-09 9:40 ` Markos Chandras
2015-07-09 9:40 ` [PATCH 19/19] MIPS: Set up FTLB probability for I6400 Markos Chandras
2015-07-09 9:40 ` Markos Chandras
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