From: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
To: <broonie@kernel.org>, <michal.simek@xilinx.com>,
<soren.brinkmann@xilinx.com>, <dwmw2@infradead.org>,
<computersforpeace@gmail.com>, <zajec5@gmail.com>,
<marex@denx.de>, <shijie.huang@intel.com>, <juhosg@openwrt.org>,
<ben@decadent.org.uk>
Cc: <linux-mtd@lists.infradead.org>, <linux-spi@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <harinik@xilinx.com>,
<punnaia@xilinx.com>, <ran27jit@gmail.com>,
Ranjit Waghmode <ranjit.waghmode@xilinx.com>
Subject: [RFC PATCH 1/2] spi: zynqmp: gqspi: add support for dual parallel mode configuration
Date: Thu, 9 Jul 2015 18:14:54 +0530 [thread overview]
Message-ID: <1436445895-25504-2-git-send-email-ranjit.waghmode@xilinx.com> (raw)
In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com>
This patch adds support of dual parallel mode configuration for
Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
---
drivers/spi/spi-zynqmp-gqspi.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 87b20a5..271fa80 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -153,6 +153,7 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
* @dma_rx_bytes: Remaining bytes to receive by DMA mode
* @dma_addr: DMA address after mapping the kernel buffer
* @genfifoentry: Used for storing the genfifoentry instruction.
+ * @isinstr: To determine whether the transfer is instruction
* @mode: Defines the mode in which QSPI is operating
*/
struct zynqmp_qspi {
@@ -170,6 +171,7 @@ struct zynqmp_qspi {
u32 dma_rx_bytes;
dma_addr_t dma_addr;
u32 genfifoentry;
+ bool isinstr;
enum mode_type mode;
};
@@ -404,9 +406,20 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
genfifoentry |= xqspi->genfifobus;
+ if (qspi->master->flags & SPI_BOTH_FLASH) {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_BOTH,
+ GQSPI_SELECT_FLASH_BUS_BOTH);
+ } else {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_LOWER,
+ GQSPI_SELECT_FLASH_BUS_LOWER);
+ }
+
if (!is_high) {
genfifoentry |= xqspi->genfifocs;
genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
+ xqspi->isinstr = true;
} else {
genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
}
@@ -663,6 +676,7 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
&& ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
+ xqspi->isinstr = false;
spi_finalize_current_transfer(master);
ret = IRQ_HANDLED;
}
@@ -826,6 +840,9 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master,
genfifoentry |= xqspi->genfifocs;
genfifoentry |= xqspi->genfifobus;
+ if ((!xqspi->isinstr) && (master->flags & SPI_DATA_STRIPE))
+ genfifoentry |= GQSPI_GENFIFO_STRIPE;
+
zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
if (xqspi->mode == GQSPI_MODE_DMA)
@@ -982,6 +999,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
struct zynqmp_qspi *xqspi;
struct resource *res;
struct device *dev = &pdev->dev;
+ u32 num_cs;
master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
if (!master)
@@ -1042,7 +1060,11 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
goto clk_dis_all;
}
- master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
+ ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
+ if (ret < 0)
+ master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
+ else
+ master->num_chipselect = num_cs;
master->setup = zynqmp_qspi_setup;
master->set_cs = zynqmp_qspi_chipselect;
--
2.1.2
WARNING: multiple messages have this Message-ID (diff)
From: ranjit.waghmode@xilinx.com (Ranjit Waghmode)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 1/2] spi: zynqmp: gqspi: add support for dual parallel mode configuration
Date: Thu, 9 Jul 2015 18:14:54 +0530 [thread overview]
Message-ID: <1436445895-25504-2-git-send-email-ranjit.waghmode@xilinx.com> (raw)
In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com>
This patch adds support of dual parallel mode configuration for
Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
---
drivers/spi/spi-zynqmp-gqspi.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 87b20a5..271fa80 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -153,6 +153,7 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
* @dma_rx_bytes: Remaining bytes to receive by DMA mode
* @dma_addr: DMA address after mapping the kernel buffer
* @genfifoentry: Used for storing the genfifoentry instruction.
+ * @isinstr: To determine whether the transfer is instruction
* @mode: Defines the mode in which QSPI is operating
*/
struct zynqmp_qspi {
@@ -170,6 +171,7 @@ struct zynqmp_qspi {
u32 dma_rx_bytes;
dma_addr_t dma_addr;
u32 genfifoentry;
+ bool isinstr;
enum mode_type mode;
};
@@ -404,9 +406,20 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
genfifoentry |= xqspi->genfifobus;
+ if (qspi->master->flags & SPI_BOTH_FLASH) {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_BOTH,
+ GQSPI_SELECT_FLASH_BUS_BOTH);
+ } else {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_LOWER,
+ GQSPI_SELECT_FLASH_BUS_LOWER);
+ }
+
if (!is_high) {
genfifoentry |= xqspi->genfifocs;
genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
+ xqspi->isinstr = true;
} else {
genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
}
@@ -663,6 +676,7 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
&& ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
+ xqspi->isinstr = false;
spi_finalize_current_transfer(master);
ret = IRQ_HANDLED;
}
@@ -826,6 +840,9 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master,
genfifoentry |= xqspi->genfifocs;
genfifoentry |= xqspi->genfifobus;
+ if ((!xqspi->isinstr) && (master->flags & SPI_DATA_STRIPE))
+ genfifoentry |= GQSPI_GENFIFO_STRIPE;
+
zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
if (xqspi->mode == GQSPI_MODE_DMA)
@@ -982,6 +999,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
struct zynqmp_qspi *xqspi;
struct resource *res;
struct device *dev = &pdev->dev;
+ u32 num_cs;
master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
if (!master)
@@ -1042,7 +1060,11 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
goto clk_dis_all;
}
- master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
+ ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
+ if (ret < 0)
+ master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
+ else
+ master->num_chipselect = num_cs;
master->setup = zynqmp_qspi_setup;
master->set_cs = zynqmp_qspi_chipselect;
--
2.1.2
WARNING: multiple messages have this Message-ID (diff)
From: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
To: <broonie@kernel.org>, <michal.simek@xilinx.com>,
<soren.brinkmann@xilinx.com>, <dwmw2@infradead.org>,
<computersforpeace@gmail.com>, <zajec5@gmail.com>,
<marex@denx.de>, <shijie.huang@intel.com>, <juhosg@openwrt.org>,
<ben@decadent.org.uk>
Cc: harinik@xilinx.com, Ranjit Waghmode <ranjit.waghmode@xilinx.com>,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
linux-mtd@lists.infradead.org, punnaia@xilinx.com,
ran27jit@gmail.com, linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 1/2] spi: zynqmp: gqspi: add support for dual parallel mode configuration
Date: Thu, 9 Jul 2015 18:14:54 +0530 [thread overview]
Message-ID: <1436445895-25504-2-git-send-email-ranjit.waghmode@xilinx.com> (raw)
In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com>
This patch adds support of dual parallel mode configuration for
Zynq Ultrascale+ MPSoC GQSPI controller driver.
Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
---
drivers/spi/spi-zynqmp-gqspi.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 87b20a5..271fa80 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -153,6 +153,7 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
* @dma_rx_bytes: Remaining bytes to receive by DMA mode
* @dma_addr: DMA address after mapping the kernel buffer
* @genfifoentry: Used for storing the genfifoentry instruction.
+ * @isinstr: To determine whether the transfer is instruction
* @mode: Defines the mode in which QSPI is operating
*/
struct zynqmp_qspi {
@@ -170,6 +171,7 @@ struct zynqmp_qspi {
u32 dma_rx_bytes;
dma_addr_t dma_addr;
u32 genfifoentry;
+ bool isinstr;
enum mode_type mode;
};
@@ -404,9 +406,20 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
genfifoentry |= xqspi->genfifobus;
+ if (qspi->master->flags & SPI_BOTH_FLASH) {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_BOTH,
+ GQSPI_SELECT_FLASH_BUS_BOTH);
+ } else {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_LOWER,
+ GQSPI_SELECT_FLASH_BUS_LOWER);
+ }
+
if (!is_high) {
genfifoentry |= xqspi->genfifocs;
genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
+ xqspi->isinstr = true;
} else {
genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
}
@@ -663,6 +676,7 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
&& ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
+ xqspi->isinstr = false;
spi_finalize_current_transfer(master);
ret = IRQ_HANDLED;
}
@@ -826,6 +840,9 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master,
genfifoentry |= xqspi->genfifocs;
genfifoentry |= xqspi->genfifobus;
+ if ((!xqspi->isinstr) && (master->flags & SPI_DATA_STRIPE))
+ genfifoentry |= GQSPI_GENFIFO_STRIPE;
+
zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
if (xqspi->mode == GQSPI_MODE_DMA)
@@ -982,6 +999,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
struct zynqmp_qspi *xqspi;
struct resource *res;
struct device *dev = &pdev->dev;
+ u32 num_cs;
master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
if (!master)
@@ -1042,7 +1060,11 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
goto clk_dis_all;
}
- master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
+ ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
+ if (ret < 0)
+ master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
+ else
+ master->num_chipselect = num_cs;
master->setup = zynqmp_qspi_setup;
master->set_cs = zynqmp_qspi_chipselect;
--
2.1.2
next prev parent reply other threads:[~2015-07-09 13:02 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-09 12:44 [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode [this message]
2015-07-09 12:44 ` [RFC PATCH 1/2] spi: zynqmp: gqspi: add support for dual parallel mode configuration Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-14 16:26 ` Mark Brown
2015-07-14 16:26 ` Mark Brown
2015-07-14 16:26 ` Mark Brown
2015-07-09 12:44 ` [RFC PATCH 2/2] spi: zynqmp: gqspi: add support for stacked " Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-14 16:28 ` Mark Brown
2015-07-14 16:28 ` Mark Brown
2015-07-14 16:28 ` Mark Brown
2015-07-10 8:28 ` [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Mike Looijmans
2015-07-10 8:28 ` Mike Looijmans
2015-07-13 14:59 ` Mark Brown
2015-07-13 14:59 ` Mark Brown
2015-07-13 14:59 ` Mark Brown
2015-07-13 10:04 ` Thomas.Betker
2015-07-13 10:04 ` Thomas.Betker
2015-07-13 10:04 ` Thomas.Betker at rohde-schwarz.com
2015-07-14 4:24 ` Harini Katakam
2015-07-14 4:24 ` Harini Katakam
2015-07-14 4:24 ` Harini Katakam
2015-07-14 16:40 ` Mark Brown
2015-07-14 16:40 ` Mark Brown
2015-07-14 16:40 ` Mark Brown
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 16:01 ` Mark Brown
2015-07-15 16:01 ` Mark Brown
2015-07-15 16:01 ` Mark Brown
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 8:57 ` Mark Brown
2015-07-16 8:57 ` Mark Brown
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:42 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:42 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:52 ` Mark Brown
2015-07-24 10:52 ` Mark Brown
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 14:23 ` Mark Brown
2015-07-27 14:23 ` Mark Brown
2015-07-27 14:23 ` Mark Brown
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