From: Mark Brown <broonie@kernel.org>
To: Mike Looijmans <mike.looijmans@topic.nl>
Cc: Ranjit Waghmode <ranjit.waghmode@xilinx.com>,
michal.simek@xilinx.com, soren.brinkmann@xilinx.com,
dwmw2@infradead.org, computersforpeace@gmail.com,
zajec5@gmail.com, marex@denx.de, shijie.huang@intel.com,
juhosg@openwrt.org, ben@decadent.org.uk, harinik@xilinx.com,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
linux-mtd@lists.infradead.org, punnaia@xilinx.com,
ran27jit@gmail.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Date: Mon, 13 Jul 2015 15:59:07 +0100 [thread overview]
Message-ID: <20150713145907.GF11162@sirena.org.uk> (raw)
In-Reply-To: <559F824B.70409@topic.nl>
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On Fri, Jul 10, 2015 at 10:28:59AM +0200, Mike Looijmans wrote:
> On 09-07-15 14:44, Ranjit Waghmode wrote:
> >ZynqMP GQSPI controller supports stacked mode with following functionalities:
> >1) The Generic Quad-SPI controller also supports two SPI flash memories
> > in a shared bus arrangement to reduce IO pin count.
> >2) Separate chip select lines
> >3) Shared I/O lines
> >4) This mode is targeted for increasing the flash memory and no performance
> > improvement when compared with single.
> One could also model the stacked mode as having two distinct flash chips
> with separate chip selects and shared lines.
Well, quite. I'm confused about how the above differs from a just a SPI
controller with two chip selects which is perfectly standard.
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From: broonie@kernel.org (Mark Brown)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Date: Mon, 13 Jul 2015 15:59:07 +0100 [thread overview]
Message-ID: <20150713145907.GF11162@sirena.org.uk> (raw)
In-Reply-To: <559F824B.70409@topic.nl>
On Fri, Jul 10, 2015 at 10:28:59AM +0200, Mike Looijmans wrote:
> ?On 09-07-15 14:44, Ranjit Waghmode wrote:
> >ZynqMP GQSPI controller supports stacked mode with following functionalities:
> >1) The Generic Quad-SPI controller also supports two SPI flash memories
> > in a shared bus arrangement to reduce IO pin count.
> >2) Separate chip select lines
> >3) Shared I/O lines
> >4) This mode is targeted for increasing the flash memory and no performance
> > improvement when compared with single.
> One could also model the stacked mode as having two distinct flash chips
> with separate chip selects and shared lines.
Well, quite. I'm confused about how the above differs from a just a SPI
controller with two chip selects which is perfectly standard.
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From: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Mike Looijmans <mike.looijmans-Oq418RWZeHk@public.gmane.org>
Cc: Ranjit Waghmode
<ranjit.waghmode-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>,
michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org,
soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org,
dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org,
computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
marex-ynQEQJNshbs@public.gmane.org,
shijie.huang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org,
ben-/+tVBieCtBitmTQ+vhA3Yw@public.gmane.org,
harinik-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org,
ran27jit-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Date: Mon, 13 Jul 2015 15:59:07 +0100 [thread overview]
Message-ID: <20150713145907.GF11162@sirena.org.uk> (raw)
In-Reply-To: <559F824B.70409-Oq418RWZeHk@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 783 bytes --]
On Fri, Jul 10, 2015 at 10:28:59AM +0200, Mike Looijmans wrote:
> On 09-07-15 14:44, Ranjit Waghmode wrote:
> >ZynqMP GQSPI controller supports stacked mode with following functionalities:
> >1) The Generic Quad-SPI controller also supports two SPI flash memories
> > in a shared bus arrangement to reduce IO pin count.
> >2) Separate chip select lines
> >3) Shared I/O lines
> >4) This mode is targeted for increasing the flash memory and no performance
> > improvement when compared with single.
> One could also model the stacked mode as having two distinct flash chips
> with separate chip selects and shared lines.
Well, quite. I'm confused about how the above differs from a just a SPI
controller with two chip selects which is perfectly standard.
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next prev parent reply other threads:[~2015-07-13 14:59 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-09 12:44 [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` [RFC PATCH 1/2] spi: zynqmp: gqspi: add support for dual parallel mode configuration Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-14 16:26 ` Mark Brown
2015-07-14 16:26 ` Mark Brown
2015-07-14 16:26 ` Mark Brown
2015-07-09 12:44 ` [RFC PATCH 2/2] spi: zynqmp: gqspi: add support for stacked " Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-14 16:28 ` Mark Brown
2015-07-14 16:28 ` Mark Brown
2015-07-14 16:28 ` Mark Brown
2015-07-10 8:28 ` [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Mike Looijmans
2015-07-10 8:28 ` Mike Looijmans
2015-07-13 14:59 ` Mark Brown [this message]
2015-07-13 14:59 ` Mark Brown
2015-07-13 14:59 ` Mark Brown
2015-07-13 10:04 ` Thomas.Betker
2015-07-13 10:04 ` Thomas.Betker
2015-07-13 10:04 ` Thomas.Betker at rohde-schwarz.com
2015-07-14 4:24 ` Harini Katakam
2015-07-14 4:24 ` Harini Katakam
2015-07-14 4:24 ` Harini Katakam
2015-07-14 16:40 ` Mark Brown
2015-07-14 16:40 ` Mark Brown
2015-07-14 16:40 ` Mark Brown
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 16:01 ` Mark Brown
2015-07-15 16:01 ` Mark Brown
2015-07-15 16:01 ` Mark Brown
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 8:57 ` Mark Brown
2015-07-16 8:57 ` Mark Brown
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:42 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:42 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:52 ` Mark Brown
2015-07-24 10:52 ` Mark Brown
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 14:23 ` Mark Brown
2015-07-27 14:23 ` Mark Brown
2015-07-27 14:23 ` Mark Brown
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