From: Thomas.Betker@rohde-schwarz.com
To: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
Cc: ben@decadent.org.uk, broonie@kernel.org,
computersforpeace@gmail.com, dwmw2@infradead.org,
harinik@xilinx.com, juhosg@openwrt.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
"linux-mtd" <linux-mtd-bounces@lists.infradead.org>,
linux-spi@vger.kernel.org, marex@denx.de,
michal.simek@xilinx.com, punnaia@xilinx.com, ran27jit@gmail.com,
shijie.huang@intel.com, soren.brinkmann@xilinx.com,
zajec5@gmail.com
Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Date: Mon, 13 Jul 2015 12:04:54 +0200 [thread overview]
Message-ID: <OFDDDA0AA7.A583461A-ONC1257E81.0030FCED-C1257E81.003761EE@rohde-schwarz.com> (raw)
In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com>
Hello Ranjit:
> What is dual parallel mode?
> ---------------------------
> ZynqMP GQSPI controller supports Dual Parallel mode with following
> functionalities:
> 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines.
> 2) Chip selects and clock are shared to both the flash devices
> 3) This mode is targeted for faster read/write speed and also doubles
the size
> 4) Commands/data can be transmitted/received from both the
devices(mirror),
> or only upper or only lower flash memory devices.
> 5) Data arrangement:
> With stripe enabled,
> Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus
> Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus.
In the dual-parallel configuration, odd and even _bits_ of each byte are
distributed over the flash chips; I am assuming this works just as in Zynq
QSPI (apparently, the TRM for ZynqMP isn't out yet).
Striping seems to be a different mechanism, though. Can you explain it a
bit more? Also, the wording seems to indicate that it belongs to
dual-stacked rather than dual-parallel.
> Suggestions on MTD layer support
> --------------------------------
> In order to add above two specified modes, we may required to get some
> support from MTD layer.
>
> I'm trying to list the dependencies as follows:
> 1) Support for two flashes
> 2) Enable/Disable data stripe as and when required.
> 3) May need to update read_sr() to get status of both flashes
> 4) May also need to update read_fsr() to get status of both flashes
> 5) Adjustment of offset value based on the parallel/stacked mode
configuration
> 6) Setting either parallel or stacked mode during the scan process.
> 7) In case of stacked mode, is there a MTD concatenation support?
In addition to 5), the MTD driver using a dual-parallel QSPI flash has to
5a) add padding at the start of data for unaligned addresses,
5b) add padding at the end of data for unaligned lengths.
Best regards,
Thomas Betker
WARNING: multiple messages have this Message-ID (diff)
From: Thomas.Betker@rohde-schwarz.com (Thomas.Betker at rohde-schwarz.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Date: Mon, 13 Jul 2015 12:04:54 +0200 [thread overview]
Message-ID: <OFDDDA0AA7.A583461A-ONC1257E81.0030FCED-C1257E81.003761EE@rohde-schwarz.com> (raw)
In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com>
Hello Ranjit:
> What is dual parallel mode?
> ---------------------------
> ZynqMP GQSPI controller supports Dual Parallel mode with following
> functionalities:
> 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines.
> 2) Chip selects and clock are shared to both the flash devices
> 3) This mode is targeted for faster read/write speed and also doubles
the size
> 4) Commands/data can be transmitted/received from both the
devices(mirror),
> or only upper or only lower flash memory devices.
> 5) Data arrangement:
> With stripe enabled,
> Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus
> Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus.
In the dual-parallel configuration, odd and even _bits_ of each byte are
distributed over the flash chips; I am assuming this works just as in Zynq
QSPI (apparently, the TRM for ZynqMP isn't out yet).
Striping seems to be a different mechanism, though. Can you explain it a
bit more? Also, the wording seems to indicate that it belongs to
dual-stacked rather than dual-parallel.
> Suggestions on MTD layer support
> --------------------------------
> In order to add above two specified modes, we may required to get some
> support from MTD layer.
>
> I'm trying to list the dependencies as follows:
> 1) Support for two flashes
> 2) Enable/Disable data stripe as and when required.
> 3) May need to update read_sr() to get status of both flashes
> 4) May also need to update read_fsr() to get status of both flashes
> 5) Adjustment of offset value based on the parallel/stacked mode
configuration
> 6) Setting either parallel or stacked mode during the scan process.
> 7) In case of stacked mode, is there a MTD concatenation support?
In addition to 5), the MTD driver using a dual-parallel QSPI flash has to
5a) add padding at the start of data for unaligned addresses,
5b) add padding at the end of data for unaligned lengths.
Best regards,
Thomas Betker
WARNING: multiple messages have this Message-ID (diff)
From: Thomas.Betker@rohde-schwarz.com
To: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
Cc: linux-mtd <linux-mtd-bounces@lists.infradead.org>,
harinik@xilinx.com, marex@denx.de, ben@decadent.org.uk,
zajec5@gmail.com, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org, juhosg@openwrt.org,
broonie@kernel.org, linux-mtd@lists.infradead.org,
soren.brinkmann@xilinx.com, shijie.huang@intel.com,
punnaia@xilinx.com, ran27jit@gmail.com,
computersforpeace@gmail.com, dwmw2@infradead.org,
michal.simek@xilinx.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Date: Mon, 13 Jul 2015 12:04:54 +0200 [thread overview]
Message-ID: <OFDDDA0AA7.A583461A-ONC1257E81.0030FCED-C1257E81.003761EE@rohde-schwarz.com> (raw)
In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com>
Hello Ranjit:
> What is dual parallel mode?
> ---------------------------
> ZynqMP GQSPI controller supports Dual Parallel mode with following
> functionalities:
> 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines.
> 2) Chip selects and clock are shared to both the flash devices
> 3) This mode is targeted for faster read/write speed and also doubles
the size
> 4) Commands/data can be transmitted/received from both the
devices(mirror),
> or only upper or only lower flash memory devices.
> 5) Data arrangement:
> With stripe enabled,
> Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus
> Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus.
In the dual-parallel configuration, odd and even _bits_ of each byte are
distributed over the flash chips; I am assuming this works just as in Zynq
QSPI (apparently, the TRM for ZynqMP isn't out yet).
Striping seems to be a different mechanism, though. Can you explain it a
bit more? Also, the wording seems to indicate that it belongs to
dual-stacked rather than dual-parallel.
> Suggestions on MTD layer support
> --------------------------------
> In order to add above two specified modes, we may required to get some
> support from MTD layer.
>
> I'm trying to list the dependencies as follows:
> 1) Support for two flashes
> 2) Enable/Disable data stripe as and when required.
> 3) May need to update read_sr() to get status of both flashes
> 4) May also need to update read_fsr() to get status of both flashes
> 5) Adjustment of offset value based on the parallel/stacked mode
configuration
> 6) Setting either parallel or stacked mode during the scan process.
> 7) In case of stacked mode, is there a MTD concatenation support?
In addition to 5), the MTD driver using a dual-parallel QSPI flash has to
5a) add padding at the start of data for unaligned addresses,
5b) add padding at the end of data for unaligned lengths.
Best regards,
Thomas Betker
next prev parent reply other threads:[~2015-07-13 10:20 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-09 12:44 [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` [RFC PATCH 1/2] spi: zynqmp: gqspi: add support for dual parallel mode configuration Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-14 16:26 ` Mark Brown
2015-07-14 16:26 ` Mark Brown
2015-07-14 16:26 ` Mark Brown
2015-07-09 12:44 ` [RFC PATCH 2/2] spi: zynqmp: gqspi: add support for stacked " Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-14 16:28 ` Mark Brown
2015-07-14 16:28 ` Mark Brown
2015-07-14 16:28 ` Mark Brown
2015-07-10 8:28 ` [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Mike Looijmans
2015-07-10 8:28 ` Mike Looijmans
2015-07-13 14:59 ` Mark Brown
2015-07-13 14:59 ` Mark Brown
2015-07-13 14:59 ` Mark Brown
2015-07-13 10:04 ` Thomas.Betker [this message]
2015-07-13 10:04 ` Thomas.Betker
2015-07-13 10:04 ` Thomas.Betker at rohde-schwarz.com
2015-07-14 4:24 ` Harini Katakam
2015-07-14 4:24 ` Harini Katakam
2015-07-14 4:24 ` Harini Katakam
2015-07-14 16:40 ` Mark Brown
2015-07-14 16:40 ` Mark Brown
2015-07-14 16:40 ` Mark Brown
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 16:01 ` Mark Brown
2015-07-15 16:01 ` Mark Brown
2015-07-15 16:01 ` Mark Brown
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 8:57 ` Mark Brown
2015-07-16 8:57 ` Mark Brown
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:42 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:42 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:52 ` Mark Brown
2015-07-24 10:52 ` Mark Brown
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 14:23 ` Mark Brown
2015-07-27 14:23 ` Mark Brown
2015-07-27 14:23 ` Mark Brown
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