From: Ranjit Abhimanyu Waghmode <ranjit.waghmode@xilinx.com>
To: Mark Brown <broonie@kernel.org>
Cc: Michal Simek <michals@xilinx.com>,
Soren Brinkmann <sorenb@xilinx.com>,
"dwmw2@infradead.org" <dwmw2@infradead.org>,
"computersforpeace@gmail.com" <computersforpeace@gmail.com>,
"zajec5@gmail.com" <zajec5@gmail.com>,
"marex@denx.de" <marex@denx.de>,
"shijie.huang@intel.com" <shijie.huang@intel.com>,
"juhosg@openwrt.org" <juhosg@openwrt.org>,
"ben@decadent.org.uk" <ben@decadent.org.uk>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Harini Katakam <harinik@xilinx.com>,
"Punnaiah Choudary Kalluri" <punnaia@xilinx.com>,
"ran27jit@gmail.com" <ran27jit@gmail.com>
Subject: RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Date: Wed, 15 Jul 2015 14:12:54 +0000 [thread overview]
Message-ID: <7CFCFE83B8145347A1D424EC939F1C3CA7E53D@XAP-PVEXMBX01.xlnx.xilinx.com> (raw)
In-Reply-To: <20150714164005.GE11162@sirena.org.uk>
Hi Mark,
> > What is dual parallel mode?
> > ---------------------------
> > ZynqMP GQSPI controller supports Dual Parallel mode with following
> functionalities:
> > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines.
> > 2) Chip selects and clock are shared to both the flash devices
> > 3) This mode is targeted for faster read/write speed and also doubles the size
> > 4) Commands/data can be transmitted/received from both the devices(mirror),
> > or only upper or only lower flash memory devices.
> > 5) Data arrangement:
> > With stripe enabled,
> > Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus
> > Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus.
>
> For the SPI code this just seems like SPI with an 8 bit data width.
>
> > What is stacked mode?
> > ---------------------
> > ZynqMP GQSPI controller supports stacked mode with following
> functionalities:
> > 1) The Generic Quad-SPI controller also supports two SPI flash memories
> > in a shared bus arrangement to reduce IO pin count.
> > 2) Separate chip select lines
> > 3) Shared I/O lines
> > 4) This mode is targeted for increasing the flash memory and no performance
> > improvement when compared with single.
>
> This is just a normal SPI controller from a SPI point of view.
How can we really represent the stacked mode in current configuration?
Thanks & Regards,
Ranjit
WARNING: multiple messages have this Message-ID (diff)
From: ranjit.waghmode@xilinx.com (Ranjit Abhimanyu Waghmode)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Date: Wed, 15 Jul 2015 14:12:54 +0000 [thread overview]
Message-ID: <7CFCFE83B8145347A1D424EC939F1C3CA7E53D@XAP-PVEXMBX01.xlnx.xilinx.com> (raw)
In-Reply-To: <20150714164005.GE11162@sirena.org.uk>
Hi Mark,
> > What is dual parallel mode?
> > ---------------------------
> > ZynqMP GQSPI controller supports Dual Parallel mode with following
> functionalities:
> > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines.
> > 2) Chip selects and clock are shared to both the flash devices
> > 3) This mode is targeted for faster read/write speed and also doubles the size
> > 4) Commands/data can be transmitted/received from both the devices(mirror),
> > or only upper or only lower flash memory devices.
> > 5) Data arrangement:
> > With stripe enabled,
> > Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus
> > Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus.
>
> For the SPI code this just seems like SPI with an 8 bit data width.
>
> > What is stacked mode?
> > ---------------------
> > ZynqMP GQSPI controller supports stacked mode with following
> functionalities:
> > 1) The Generic Quad-SPI controller also supports two SPI flash memories
> > in a shared bus arrangement to reduce IO pin count.
> > 2) Separate chip select lines
> > 3) Shared I/O lines
> > 4) This mode is targeted for increasing the flash memory and no performance
> > improvement when compared with single.
>
> This is just a normal SPI controller from a SPI point of view.
How can we really represent the stacked mode in current configuration?
Thanks & Regards,
Ranjit
WARNING: multiple messages have this Message-ID (diff)
From: Ranjit Abhimanyu Waghmode <ranjit.waghmode@xilinx.com>
To: Mark Brown <broonie@kernel.org>
Cc: "marex@denx.de" <marex@denx.de>,
Harini Katakam <harinik@xilinx.com>,
"ben@decadent.org.uk" <ben@decadent.org.uk>,
"zajec5@gmail.com" <zajec5@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
"juhosg@openwrt.org" <juhosg@openwrt.org>,
Michal Simek <michals@xilinx.com>,
Soren Brinkmann <sorenb@xilinx.com>,
Punnaiah Choudary Kalluri <punnaia@xilinx.com>,
"shijie.huang@intel.com" <shijie.huang@intel.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"ran27jit@gmail.com" <ran27jit@gmail.com>,
"computersforpeace@gmail.com" <computersforpeace@gmail.com>,
"dwmw2@infradead.org" <dwmw2@infradead.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: RE: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller
Date: Wed, 15 Jul 2015 14:12:54 +0000 [thread overview]
Message-ID: <7CFCFE83B8145347A1D424EC939F1C3CA7E53D@XAP-PVEXMBX01.xlnx.xilinx.com> (raw)
In-Reply-To: <20150714164005.GE11162@sirena.org.uk>
Hi Mark,
> > What is dual parallel mode?
> > ---------------------------
> > ZynqMP GQSPI controller supports Dual Parallel mode with following
> functionalities:
> > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines.
> > 2) Chip selects and clock are shared to both the flash devices
> > 3) This mode is targeted for faster read/write speed and also doubles the size
> > 4) Commands/data can be transmitted/received from both the devices(mirror),
> > or only upper or only lower flash memory devices.
> > 5) Data arrangement:
> > With stripe enabled,
> > Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus
> > Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus.
>
> For the SPI code this just seems like SPI with an 8 bit data width.
>
> > What is stacked mode?
> > ---------------------
> > ZynqMP GQSPI controller supports stacked mode with following
> functionalities:
> > 1) The Generic Quad-SPI controller also supports two SPI flash memories
> > in a shared bus arrangement to reduce IO pin count.
> > 2) Separate chip select lines
> > 3) Shared I/O lines
> > 4) This mode is targeted for increasing the flash memory and no performance
> > improvement when compared with single.
>
> This is just a normal SPI controller from a SPI point of view.
How can we really represent the stacked mode in current configuration?
Thanks & Regards,
Ranjit
next prev parent reply other threads:[~2015-07-15 14:28 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-09 12:44 [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` [RFC PATCH 1/2] spi: zynqmp: gqspi: add support for dual parallel mode configuration Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-14 16:26 ` Mark Brown
2015-07-14 16:26 ` Mark Brown
2015-07-14 16:26 ` Mark Brown
2015-07-09 12:44 ` [RFC PATCH 2/2] spi: zynqmp: gqspi: add support for stacked " Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-09 12:44 ` Ranjit Waghmode
2015-07-14 16:28 ` Mark Brown
2015-07-14 16:28 ` Mark Brown
2015-07-14 16:28 ` Mark Brown
2015-07-10 8:28 ` [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Mike Looijmans
2015-07-10 8:28 ` Mike Looijmans
2015-07-13 14:59 ` Mark Brown
2015-07-13 14:59 ` Mark Brown
2015-07-13 14:59 ` Mark Brown
2015-07-13 10:04 ` Thomas.Betker
2015-07-13 10:04 ` Thomas.Betker
2015-07-13 10:04 ` Thomas.Betker at rohde-schwarz.com
2015-07-14 4:24 ` Harini Katakam
2015-07-14 4:24 ` Harini Katakam
2015-07-14 4:24 ` Harini Katakam
2015-07-14 16:40 ` Mark Brown
2015-07-14 16:40 ` Mark Brown
2015-07-14 16:40 ` Mark Brown
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode [this message]
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 14:12 ` Ranjit Abhimanyu Waghmode
2015-07-15 16:01 ` Mark Brown
2015-07-15 16:01 ` Mark Brown
2015-07-15 16:01 ` Mark Brown
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 7:27 ` Ranjit Abhimanyu Waghmode
2015-07-16 8:57 ` Mark Brown
2015-07-16 8:57 ` Mark Brown
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-17 12:03 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:42 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:42 ` Ranjit Abhimanyu Waghmode
2015-07-24 10:52 ` Mark Brown
2015-07-24 10:52 ` Mark Brown
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 13:55 ` Ranjit Abhimanyu Waghmode
2015-07-27 14:23 ` Mark Brown
2015-07-27 14:23 ` Mark Brown
2015-07-27 14:23 ` Mark Brown
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